I have been debugging a hardfault in example "S32K344_CAN_Bootloader_RTD2d0" . I find out that the exceptions was no activated, after do it, busfault handler and memfault handler are called.
It seems to be a problem in the PLL because it is locked I dont know why, and the program is continuously doing the clock initialization until the exceptions appears.
There are some dummy functions in the example that I don´t change, must I complete any configuration in this functions?
for example this one
Solved! Go to Solution.
Hi, I am using the project "S32K344_Can_bootloader_RTD200" in the microprocessor S32K344. I want to download an application with the program of bootloader. I have achieved the jump from program to application but I have different questions. 1. I want to use #define EN_DELAY_TIME but when I uncomment the command in the folder "public_in", the program has different errors. My target to use "Backdoor", that is to say, I want to check if the program has to enter to bootloader or not. I don´t know the process and the different functions that I have to use to achieve the target. I want to use the function "Boot_CheckReqBootloaderMode(void)" but when I debug the program, it never enters to the "if". Could you explain me the process and the steps to achieve the target. I add different functions that I think are important. 2. I don´t know if I have to modificate the parameters of "static tJumpAppDelayTimeInfo gs_stJumpAPPDelayTimeInfo = {FALSE, 0u};". I have to change this structure ? You can see all structure in one of the next pictures. I need the reply as soon as possible since I have to send a project very soon.
Thank you for all,
Hi
S32K344_CAN_Bootloader_RTD2d0 example is not developed based on S32K3-T-BOX. So you may need to modify the configuration according to S32K3-T-BOX.
For example: Crystal Y2 on S32K3-T-BOX is 40MHz. But in this example it is configured as 16MHz.
Best Regards,
Robin
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It is already changed, but still have the same problem.
Are there more configurations to do?
Please enable the clock gate of PLL.