S32K396_ATO_Data transmission and event triggering

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S32K396_ATO_Data transmission and event triggering

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Zhougw
Contributor III

After I read the datasheet and demo code, I still have a lot of confusion about the how ATO is implemented.

Now, I know eTPU trigger SWG(phase control), DSPSS get data from SDADC, DMA trasfer sin/cos data from DSPSS to eTPU. CPU get angle and speed by calling fs_etpu_resolver_get_outputs_extrapolated function.
but I still have a lot of confusion about the details.

1. How to make sure eTPU trigger is in Phase alignement acceptance window of SWG(SGEN)?
2. Do I need to enable FIFO in SDADC for transfer data from SDADC to DSPSS? In demo code, fifoThreshold is 8, but I think there should be 32 SIN/COS data to transfer, and I didn't see any description in DSPSS chapter of datasheet.
3. In dsp_init function, INPUT_THRESHOLD is 20, OUTPUT_THRESHOLD is 8, I don't get it, shouldn't that be 32? since DMA ransfer 32 data from DSPSS to eTPU.
4. How to trigger ATO calculation in eTPU, by HSR? but in demo code, DMA transfer data from sResolverExcCmdDspBuf to HSRR, sResolverExcCmdDspBuf is an array, and HSRR is not, how did that work?
5. etpu_set.zip download from https://www.nxp.com/webapp/etpu_cw/ is not right. etpu_gct.c call Undeclared functions, fs_memset32 and fs_etpu_init only exist in old etpu_set.zip, but the new etpu_set.zip still call this function, I think it should call Etpu_Ip_MemsetU32 and Etpu_Ip_Init. I am not sure if the code have been tested.

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danielmartynek
NXP TechSupport
NXP TechSupport

Hello @Zhougw,

The S32K39x series is an NPI, and all its documentation it is acceptable under an NDA.

If you have access to the devices, your company has probably NXP FAEs assigned, please contact them.

Otherwise, create a ticket from an account with your company email domain.

 

Thank you,

BR, Daniel

 

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