S32K344: Unable to generate complementary PWM signals with 200 Hz in OPWMB mode

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S32K344: Unable to generate complementary PWM signals with 200 Hz in OPWMB mode

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ManishKK
Contributor III

Hello,

I am using MR-CANHUB board with S32K344 in Q172 package config and S32DS IDE.

I have to generate resolver PWM signals and their complementary with 200 Hz and 20% duty-cycle.

I was able to get the 20% duty-cycle working. However, the freq of the signal is around 147 Hz, instead of 200 Hz.

On the attached logic analyzer capture - Ch11 - PTA0, Ch12 - PTA1, Ch 13 - PTA2 and CH14 - PTA3.

PTA1 is complementary of PTA0 and PTA2 is complementary of PTA3. In other words, PTA1 is inverted of PTA0 and PTA2 is inverted of PTA3. Both PTA3 and PTA2 are generating PWMs at fixed - 200Hz and 20% duty-cycle.

Here is the calculation, I did to get 200 Hz (which is not working) and 20% dc.

CoreClk = 48 Mhz

Using this formula: PWM frequency = CORE_CLK / global prescaler / internal prescaler / (B1+1), I have the following settings:

             200 Hz = 48 Mhz / 16 / 6 / (2499 + 1)

However, what I get is ~147 Hz.

Please tell me what I may have missed. Also attaching code for reference.

 

 

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1 Solution
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ManishKK
Contributor III

I got it working. I had some example code that was setting the period of CH23 global counter to wrong values. Same with the duty cycle of the 4 channels,  these were set wrongly as well.

To get 200 Hz in OPWMB mode, I set the global prescaler to 16 and local prescaler to 16 as well. Now I needed to divide by 15000 to get to 200Hz.

For 20% duty-cycle, I just the set the duty cycle to 20% of 15000, which is 3000. Attaching the example code for future re-use.

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7 Replies
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ManishKK
Contributor III

Robin, changing from FIRC to PLL_PHI0 seems quite complicated. This is because:

  • The PLL is inactive.
  • Peripherals like the Ethernet/MAC, SPI, CAN are dependent on Core_CLK. So changing this will affect all subsystems.

Another confusion is - how is changing to PLL_PHI0 going to help PWM run at a fixed frequency of 200Hz. Are there peripherals that behave differently based on Clock source. Any way, you can point me to a section of the documentation that deals with this.

Many thanks!

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3,024 Views
ManishKK
Contributor III

I got it working. I had some example code that was setting the period of CH23 global counter to wrong values. Same with the duty cycle of the 4 channels,  these were set wrongly as well.

To get 200 Hz in OPWMB mode, I set the global prescaler to 16 and local prescaler to 16 as well. Now I needed to divide by 15000 to get to 200Hz.

For 20% duty-cycle, I just the set the duty cycle to 20% of 15000, which is 3000. Attaching the example code for future re-use.

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Robin_Shen
NXP TechSupport
NXP TechSupport

Thanks for the feedback.

Note Clock prescaler Will only have an effect in OPWFMB and OPMCB modes. Since OPWMB mode is selected, only global prescaler(Master Bus Prescaler) DIV_16 is active.

Clock prescaler Will only have an effect in OPWFMB and OPMCB modes.png

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ManishKK
Contributor III

Thanks Robin. I missed that. Good catch!

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ManishKK
Contributor III

Robin,

Hi.

 

How do I get an exact value of 200 Hz with a 20% duty-cycle? I get around 201.207 Hz.

I set the global counter to 14999 and the 20% duty-cycle of it as 2999 and it still does not come out to be exact 200 Hz.

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2,933 Views
Robin_Shen
NXP TechSupport
NXP TechSupport

Your project select FIRC as clock source of CORE_CLK(eMIOS clock source), please select PLL.

CORE_CLK PLL_PHI0.png

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ManishKK
Contributor III

Thanks selection of PLL worked!

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