S32K142 HSRUN Clock config error

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S32K142 HSRUN Clock config error

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578件の閲覧回数
Sunj
Contributor II

Hello everyone,

when i want use config HSRUN at 112M clock, i face some problem.

I refer to the instructions of S32K1XX RM 40.4.3.3. If i use the code in the example of S32DS Example Projects for S32K1xx/S32K142_Project_Hello, it happens bus fault. However, when i use the same code in SDK example, the error is missed. I want to use it without SDK. Please tell me the reason if you know, thanks very much.

 

I use the S32K142EVB, s32 design studio for arm 2.2 and use the opensda.

I uploaded the project.

Following is my clock config code:

void Mode_HSRUN_Clock_Init(void) {
SOSC_init_8MHz();
Handle_For_HSRUN();
SPLL_init_112MHz();
HighSpeedRUNmode_112MHz();
}

void SOSC_init_8MHz(void)
{
/*!
* SOSC Initialization (8 MHz):
* ===================================================
*/
SCG->SOSCDIV = SCG_SOSCDIV_SOSCDIV1(1)|
SCG_SOSCDIV_SOSCDIV2(1); /* SOSCDIV1 & SOSCDIV2 =1: divide by 1 */
SCG->SOSCCFG = SCG_SOSCCFG_RANGE(2)| /* Range=2: Medium freq (SOSC betw 1MHz-8MHz) */
SCG_SOSCCFG_EREFS_MASK; /* HGO=0: Config xtal osc for low power */
/* EREFS=1: Input is external XTAL */

while(SCG->SOSCCSR & SCG_SOSCCSR_LK_MASK); /* Ensure SOSCCSR unlocked */
SCG->SOSCCSR = SCG_SOSCCSR_SOSCEN_MASK; /* LK=0: SOSCCSR can be written */
/* SOSCCMRE=0: OSC CLK monitor IRQ if enabled */
/* SOSCCM=0: OSC CLK monitor disabled */
/* SOSCERCLKEN=0: Sys OSC 3V ERCLK output clk disabled */
/* SOSCLPEN=0: Sys OSC disabled in VLP modes */
/* SOSCSTEN=0: Sys OSC disabled in Stop modes */
/* SOSCEN=1: Enable oscillator */

while(!(SCG->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK)); /* Wait for sys OSC clk valid */
}

 

void Handle_For_HSRUN(void) {
while (SCG->SPLLCSR & SCG_SPLLCSR_LK_MASK); //Ensure SPLLCSR Unlocked

SCG->SPLLCSR = 0x00000000; // disable SPLL

SCG->RCCR = SCG_RCCR_SCS(3); // config FIRC as run mode clock
while (((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT) != 3); // wait success
SCG->HCCR = SCG_HCCR_SCS(3); // config FIRC as hsrun mode clock
while (((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT) != 3); // wait success

SMC->PMPROT |= SMC_PMPROT_AHSRUN_MASK; // enable hsrun mode
SMC->PMCTRL = SMC_PMCTRL_RUNM(0x03); // jump to hsrun
while (SMC->PMSTAT != 0x80);//wait jump success
}

 

void SPLL_init_112MHz(void) {
/*!
* SPLL Initialization (112 MHz):
* ===================================================
*/
while(SCG->SPLLCSR & SCG_SPLLCSR_LK_MASK); /* Ensure SPLLCSR unlocked */
SCG->SPLLCSR &= ~SCG_SPLLCSR_SPLLEN_MASK; /* SPLLEN=0: SPLL is disabled (default) and can be written */

SCG->SPLLDIV |= SCG_SPLLDIV_SPLLDIV1(1)| /* SPLLDIV1 divide by 1 */
SCG_SPLLDIV_SPLLDIV2(2); /* SPLLDIV2 divide by 2 */

SCG->SPLLCFG = SCG_SPLLCFG_MULT(12); /* PREDIV=0: Divide SOSC_CLK by 0+1=1 */
/* MULT=12: Multiply sys pll by 16+12=28 */
/* SPLL_CLK = 8MHz / 1 * 28 / 2 = 112 MHz */

while(SCG->SPLLCSR & SCG_SPLLCSR_LK_MASK); /* Ensure SPLLCSR unlocked */
SCG->SPLLCSR |= SCG_SPLLCSR_SPLLEN_MASK; /* LK=0: SPLLCSR can be written */
/* SPLLCMRE=0: SPLL CLK monitor IRQ if enabled */
/* SPLLCM=0: SPLL CLK monitor disabled */
/* SPLLSTEN=0: SPLL disabled in Stop modes */
/* SPLLEN=1: Enable SPLL */

while(!(SCG->SPLLCSR & SCG_SPLLCSR_SPLLVLD_MASK)); /* Wait for SPLL valid */
}

 

void HighSpeedRUNmode_112MHz (void) {
/*! Slow IRC is enabled with high range (8 MHz) in reset.
* Enable SIRCDIV2_CLK and SIRCDIV1_CLK, divide by 1 = 8MHz
* asynchronous clock source.
* ==========================================
*/
SCG->SIRCDIV = SCG_SIRCDIV_SIRCDIV1(1)
| SCG_SIRCDIV_SIRCDIV2(1);

/*!
* Change to normal RUN mode with 8MHz SOSC, 112 MHz PLL:
* ====================================================
*/
SCG->HCCR = SCG_HCCR_SCS(6) /* Select PLL as clock source */
| SCG_HCCR_DIVCORE(0b00) /* DIVCORE=0, div. by 1: Core clock = 112/1 MHz = 112 MHz */
| SCG_HCCR_DIVBUS(0b01) /* DIVBUS=1, div. by 2: bus clock = 56 MHz */
| SCG_HCCR_DIVSLOW(0b11); /* DIVSLOW=3, div. by 4: SCG slow, flash clock= 28 MHz */

while (((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT ) != 6) {} /* Wait for sys clk src=SPLL */
}

 

 

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1 解決策
544件の閲覧回数
Robin_Shen
NXP TechSupport
NXP TechSupport

Hi Sunj,

This seems to be the same issue as Case 00523877, please refer to my answer in Case 00523877.
If you find the reason after referring to the attached project in the case, hope you can share the reason of the error here.

Best Regards,
Robin
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2 返答(返信)
545件の閲覧回数
Robin_Shen
NXP TechSupport
NXP TechSupport

Hi Sunj,

This seems to be the same issue as Case 00523877, please refer to my answer in Case 00523877.
If you find the reason after referring to the attached project in the case, hope you can share the reason of the error here.

Best Regards,
Robin
-------------------------------------------------------------------------------
Note:
- If this post answers your question, please click the "Mark Correct" button. Thank you!

- We are following threads for 7 weeks after the last post, later replies are ignored
Please open a new thread and refer to the closed one, if you have a related question at a later point in time.
-------------------------------------------------------------------------------

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537件の閲覧回数
Sunj
Contributor II

Dear Robin_Shen:

thank you very much for solving my problem. My initial code has no big problems in terms of flow. However, I have ignored the reconfiguration of FIRC. Although it is mentioned in RM that the processor will configure FIRC by default when powered on, I think this default configuration is not perfect, and the frequency of core, bus and flash needs to be rearranged. If FIRC is not reconfigured in detail, the program will report BUS fault I hope my understanding can help others.

following is the code part i changed:

 

void Handle_For_HSRUN(void) {
while (SCG->SPLLCSR & SCG_SPLLCSR_LK_MASK); //Ensure SPLLCSR Unlocked
SCG->SPLLCSR = 0x00000000; // disable SPLL


SCG->RCCR = SCG_RCCR_SCS(3)
| SCG_RCCR_DIVCORE(0x00)
| SCG_RCCR_DIVBUS(0x00)
| SCG_RCCR_DIVSLOW(0x01); // config FIRC as run mode clock
while (((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT) != 3); // wait success
SCG->HCCR = SCG_HCCR_SCS(3)
| SCG_RCCR_DIVCORE(0x00)
| SCG_RCCR_DIVBUS(0x00)
| SCG_RCCR_DIVSLOW(0x01); // config FIRC as hsrun mode clock
while (((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT) != 3); // wait success

SMC->PMPROT |= SMC_PMPROT_AHSRUN_MASK; // enable hsrun mode
SMC->PMCTRL = SMC_PMCTRL_RUNM(0x03); // jump to hsrun
while (SMC->PMSTAT != 0x80);//wait jump success
}

finally, thanks Robin_Shen again.

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