MPU Section segregation in Linker file

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MPU Section segregation in Linker file

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Lisha
Contributor II

Hii, 

I have implemented the MPU on the S32K322 controller and selected the Linker_flash_s32k322.ld file from the RTD package in the Platform folder. I divided the PFLASH section into two parts: PFLASH and SAFEOS_ROM, and also divided the SRAM section by creating another section called SAFEOS_RAM. However, when I run the code, it triggers a HardFault. I’m not sure what I missed. Can anyone help me?

 

 
ENTRY(Reset_Handler)
 
MEMORY
{
    int_pflash              : ORIGIN = 0x00400000, LENGTH = 0x001D0000    /* 2048KB - 176KB (sBAF + HSE)*/
    SAFEOS_ROM              : ORIGIN = 0x005D0000, LENGTH = 0x00004000    /* 2048KB - 176KB (sBAF + HSE)*/
    int_dflash              : ORIGIN = 0x10000000, LENGTH = 0x00020000    /* 128KB */
    int_itcm                : ORIGIN = 0x00000000, LENGTH = 0x00008000    /* 32KB */
    int_dtcm                : ORIGIN = 0x20000000, LENGTH = 0x0000F000    /* 60KB */
    int_stack_dtcm          : ORIGIN = 0x2000F000, LENGTH = 0x00001000    /* 4KB */
    int_sram                : ORIGIN = 0x20400000, LENGTH = 0x00007F00    /* 32KB, needs to include int_sram_fls_rsv */
    int_sram_fls_rsv        : ORIGIN = 0x20407F00, LENGTH = 0x00000100
    int_sram_no_cacheable   : ORIGIN = 0x20408000, LENGTH = 0x00002000    /* 16KB , needs to include int_sram_results  */
    SAFEOS_RAM        : ORIGIN = 0x2040A000, LENGTH = 0x00002000
    int_sram_shareable      : ORIGIN = 0x2040C000, LENGTH = 0x00004000    /* 16KB */
    ram_rsvd2               : ORIGIN = 0x20410000, LENGTH = 0             /* End of SRAM */
}
 
SECTIONS
{
.osrom (NOLOAD):
    {
        . = ALIGN(4);
        KEEP(*(.osrom))
        . += 0x100;
    } > SAFEOS_ROM
 
    .pflash :
    {
        KEEP(*(.boot_header))
        . = ALIGN(8192);  /* The minimum erase size of C40 Flash IP is 8kb */
        __text_start = .;
        __interrupts_init_start = .;
        KEEP(*(.intc_vector))
        . = ALIGN(4);
        __interrupts_init_end = .;
        KEEP(*(.core_loop))
        . = ALIGN(4);
        *(.startup)
        . = ALIGN(4);
        *(.systeminit)
        . = ALIGN(4);
        *(.text.startup)
        . = ALIGN(4);
        *(.text)
        *(.text*)
        . = ALIGN(4);
        *(.mcal_text)
        . = ALIGN(4);
        *(.acmcu_code_rom)
        . = ALIGN(4);
        __acfls_code_rom_start = .;
        *(.acfls_code_rom)
        . = ALIGN(4);
        __acfls_code_rom_end = .;
        __acmem_43_infls_code_rom_start = .;
        *(.acmem_43_infls_code_rom)
        . = ALIGN(4);
        __acmem_43_infls_code_rom_end = .;
        KEEP(*(.init))
        . = ALIGN(4);
        KEEP(*(.fini))
        . = ALIGN(4);
        *(.rodata)
        *(.rodata*)
        . = ALIGN(4);
        *(.mcal_const_cfg)
        . = ALIGN(4);
        *(.mcal_const)
        . = ALIGN(4);
        __init_table = .;
        KEEP(*(.init_table))
        . = ALIGN(4);
        __zero_table = .;
        KEEP(*(.zero_table))
    } > int_pflash
 
    . = ALIGN(4);
    __text_end = .;
    __sram_data_rom = __text_end;
 
    .sram_bss (NOLOAD) :
    {
        . = ALIGN(8);
        __standby_ram_begin__ = .;
        *(.standby_data)
        . = ALIGN(8);
        __standby_ram_end__ = .;
        . = ALIGN(16);
        __sram_bss_start = .;
        *(.bss)
        *(.bss*)
        . = ALIGN(16);
        *(.mcal_bss)
        . = ALIGN(4);
        __sram_bss_end = .;
    } > int_sram
 
    .sram_data : AT(__sram_data_rom)
    {
        . = ALIGN(4);
        __sram_data_begin__ = .;
        . = ALIGN(4);
        *(.ramcode)
        . = ALIGN(4);
        *(.data)
        *(.data*)
        . = ALIGN(4);
        *(.mcal_data)
        . = ALIGN(4);
        __sram_data_end__ = .;
    } > int_sram
 
    __sram_data_rom_end = __sram_data_rom + (__sram_data_end__ - __sram_data_begin__);
 
    /* heap section */
    .heap (NOLOAD):
    {
        . += ALIGN(4);
        _end = .;
        end = .;
        _heap_start = .;
        . += HEAP_SIZE;
        _heap_end = .;
    } > int_sram
 
    .acfls_code_ram :
    {
        __acfls_code_ram_start  = .;
        *(.acfls_code_ram)
        __acfls_code_ram_end   = .;
        __acmem_43_infls_code_ram_start = .;
        *(.acmem_43_infls_code_ram)
        __acmem_43_infls_code_ram_end = .;
    } > int_sram_fls_rsv
 
    __non_cacheable_data_rom = __sram_data_rom_end;
 
    .non_cacheable_data : AT(__non_cacheable_data_rom)
    {
        . = ALIGN(4);
        __non_cacheable_data_start__ = .;
        *(.mcal_data_no_cacheable)
        . = ALIGN(4);
        *(.mcal_const_no_cacheable)
        . = ALIGN(4);
        HSE_LOOP_ADDR = .;
        LONG(0x0);
        __non_cacheable_data_end__ = .;
    } > int_sram_no_cacheable
 
    __non_cacheable_data_rom_end = __non_cacheable_data_rom + (__non_cacheable_data_end__ - __non_cacheable_data_start__);
 
    .non_cacheable_bss (NOLOAD) :
    {
        . = ALIGN(16);
        __non_cacheable_bss_start = .;
        *(.mcal_bss_no_cacheable)
        . = ALIGN(4);
        __non_cacheable_bss_end = .;
    } > int_sram_no_cacheable
 
    .osram (NOLOAD):
    {
        . = ALIGN(4);
        KEEP(*(.osram))
        . += 0x100;
    } > SAFEOS_RAM
 
    __shareable_data_rom = __non_cacheable_data_rom_end;
 
    .shareable_data : AT(__shareable_data_rom)
    {
        . = ALIGN(4);
        __shareable_data_start__ = .;
        KEEP(*(.mcal_shared_data))
        . = ALIGN(4);
        __shareable_data_end__ = .;
    } > int_sram_shareable
 
    __shareable_data_rom_end = __shareable_data_rom + (__shareable_data_end__ - __shareable_data_start__);
 
    .int_vector :
    {
        . = ALIGN(2048);
        __interrupts_ram_start = .;
        . += __interrupts_init_end - __interrupts_init_start;
        . = ALIGN(4);
        __interrupts_ram_end = .;
    } > int_dtcm
 
    __tcm_data_rom = __shareable_data_rom_end;
 
    .data_tcm_data : AT(__tcm_data_rom)
    {
        . = ALIGN(4);
        __dtcm_data_start__ = .;
        *(.dtcm_data*)
        . = ALIGN(4);
        __dtcm_data_end__ = .;
    } > int_dtcm
 
    __tcm_data_rom_end = __tcm_data_rom + (__dtcm_data_end__ - __dtcm_data_start__);
 
    .bss_tcm_data (NOLOAD) :
    {
        . = ALIGN(4);
        __dtcm_bss_start__ = .;
        *(.dtcm_bss*)
        . = ALIGN(4);
        __dtcm_bss_end__ = .;
    } > int_dtcm
 
    __tcm_code_rom_start = __tcm_data_rom_end;
 
   .itcm_text : AT(__tcm_code_rom_start)
    {
        . = ALIGN(4);
        __itcm_start__ = .;
        *(.itcm_text*)
        . = ALIGN(4);
        __itcm_end__ = .;
    } > int_itcm
 
    __tcm_code_rom_end = __tcm_code_rom_start + (__itcm_end__ - __itcm_start__);
 
    .shareable_bss (NOLOAD) :
    {
        . = ALIGN(16);
        __shareable_bss_start = .;
        *(.mcal_shared_bss)
        . = ALIGN(4);
        __shareable_bss_end = .;
    } > int_sram_shareable
 
    __Stack_dtcm_end         = ORIGIN(int_stack_dtcm);
    __Stack_dtcm_start       = ORIGIN(int_stack_dtcm) + LENGTH(int_stack_dtcm);
 
    __INT_SRAM_START         = ORIGIN(int_sram);
    __INT_SRAM_END           = ORIGIN(ram_rsvd2);
 
    __INT_ITCM_START         = ORIGIN(int_itcm);
    __INT_ITCM_END           = ORIGIN(int_itcm) + LENGTH(int_itcm);
 
    __INT_DTCM_START         = ORIGIN(int_dtcm);
    __INT_DTCM_END           = ORIGIN(int_dtcm) + LENGTH(int_dtcm) + LENGTH(int_stack_dtcm);
 
    __RAM_SHAREABLE_START    = __shareable_data_start__;
    __RAM_SHAREABLE_SIZE     = 0xE;  /* 16kbyte in power of 2 */
    __ROM_SHAREABLE_START    = __shareable_data_rom;
    __ROM_SHAREABLE_END      = __shareable_data_rom_end;
    __RAM_NO_CACHEABLE_START = __non_cacheable_data_start__;
    __RAM_NO_CACHEABLE_SIZE  = 0xE;  /* 16kbyte in power of 2 */
    __ROM_NO_CACHEABLE_START = __non_cacheable_data_rom;
    __ROM_NO_CACHEABLE_END   = __non_cacheable_data_rom_end;
    __RAM_CACHEABLE_START    = __sram_data_begin__;
    __RAM_CACHEABLE_SIZE     = 0xF;  /* 32kbyte in power of 2 */
    __ROM_CACHEABLE_START    = __sram_data_rom;
    __ROM_CACHEABLE_END      = __sram_data_rom_end;
    __ROM_CODE_START         = ORIGIN(int_pflash);
    __ROM_DATA_START         = ORIGIN(int_dflash);
 
    __BSS_SRAM_START         = __sram_bss_start;
    __BSS_SRAM_END           = __sram_bss_end;
    __BSS_SRAM_SIZE          = __sram_bss_end - __sram_bss_start;
 
    __BSS_SRAM_NC_START      = __non_cacheable_bss_start;
    __BSS_SRAM_NC_SIZE       = __non_cacheable_bss_end - __non_cacheable_bss_start;
    __BSS_SRAM_NC_END        = __non_cacheable_bss_end;
 
    __BSS_SRAM_SH_START      = __shareable_bss_start;
    __BSS_SRAM_SH_SIZE       = __shareable_bss_end - __shareable_bss_start;
    __BSS_SRAM_SH_END        = __shareable_bss_end;
 
    __RAM_INTERRUPT_START    = __interrupts_ram_start;
    __INIT_INTERRUPT_START   = __interrupts_init_start;
    __INIT_INTERRUPT_END     = __interrupts_init_end;
 
    __RAM_ITCM_START         = __itcm_start__;
    __ROM_ITCM_START         = __tcm_code_rom_start;
    __ROM_ITCM_END           = __tcm_code_rom_end;
 
    __RAM_DTCM_DATA_START    = __dtcm_data_start__;
    __ROM_DTCM_DATA_START    = __tcm_data_rom;
    __ROM_DTCM_END           = __tcm_data_rom_end;
 
    __INIT_TABLE             = __init_table;
    __ZERO_TABLE             = __zero_table;
 
    __RAM_INIT               = 1;
    __ITCM_INIT              = 1;
    __DTCM_INIT              = 1;
 
    Fls_ACEraseRomStart      = __acfls_code_rom_start;
    Fls_ACEraseRomEnd        = __acfls_code_rom_end;
    Fls_ACEraseSize          = (__acfls_code_rom_end - __acfls_code_rom_start) / 4; /* Copy 4 bytes at a time*/
 
    Fls_ACWriteRomStart      = __acfls_code_rom_start;
    Fls_ACWriteRomEnd        = __acfls_code_rom_end;
    Fls_ACWriteSize          = (__acfls_code_rom_end - __acfls_code_rom_start) / 4; /* Copy 4 bytes at a time*/
 
    _ERASE_FUNC_ADDRESS_     = __acfls_code_ram_start;
    _WRITE_FUNC_ADDRESS_     = __acfls_code_ram_start;
 
    Mem_43_INFLS_ACEraseRomStart         = __acmem_43_infls_code_rom_start;
    Mem_43_INFLS_ACEraseRomEnd           = __acmem_43_infls_code_rom_end;
    Mem_43_INFLS_ACEraseSize             = ((__acmem_43_infls_code_rom_end - __acmem_43_infls_code_rom_start)+3) / 4; /* Copy 4 bytes at a time*/
 
    Mem_43_INFLS_ACWriteRomStart         = __acmem_43_infls_code_rom_start;
    Mem_43_INFLS_ACWriteRomEnd           = __acmem_43_infls_code_rom_end;
    Mem_43_INFLS_ACWriteSize             = ((__acmem_43_infls_code_rom_end - __acmem_43_infls_code_rom_start)+3) / 4; /* Copy 4 bytes at a time*/
 
    _MEM_43_INFLS_ERASE_FUNC_ADDRESS_    = __acmem_43_infls_code_ram_start;
    _MEM_43_INFLS_WRITE_FUNC_ADDRESS_    = __acmem_43_infls_code_ram_start;
 
    __ENTRY_VTABLE           = __INIT_INTERRUPT_START;
 
    __CORE0_VTOR             = __INIT_INTERRUPT_START;
    __CORE1_VTOR             = __INIT_INTERRUPT_START;
    __CORE2_VTOR             = __INIT_INTERRUPT_START;
 
    __INDEX_COPY_CORE2       = 3;    /* This symbol is used to initialize data of ITCM/DTCM for CORE2 */
 
    ASSERT(__standby_ram_end__ <= __STANDBY_RAM_LIMIT_END, "Memory for standby ram overflow")
 
}

 

BR,

Lisha

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IsaulO
NXP Employee
NXP Employee

Hi @Lisha ,

Could you check where the Hardfault is occurring?
Check the following example about using the Hardfault handling:
Example S32K312 HARDFAULT Handling Interrupt DS3.5 RTD300 - NXP Community

Also, if you are using an RTD example the default MPU configuration in system.c is just an example, so you need to check the attributes and permissions of your memory regions and adjust them to the application. Because when an access violates the MPU permissions, the processor generates a MemManage fault and escalates to Hardfault.

BR,
IsaulO.

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