I'm developing a baremetal application and I'm thinking to put the mcu in sleep mode when idle using the WFI instruction.
As far as I understand, when calling WFI with mcu in RUN mode and DEEPSLEEP register set to 0, the mcu just goes to sleep (no STOP1 or STOP2 mode involved), is it correct?
I'm trying to figure out what's the behaviour of other peripherals when the mcu is in sleep: is there any operation that needs to be terminated before going to sleep?
For example, is it safe to call a WFI when there is an eeeprom write running at the same time?
Thanks and regards,
Hello, thanks for the answer.
I read the paragraphs, but I'm still not sure what to do.
Let me explain what i would like to do in my application. I want to measure the time the CPU remains idle, so my idea was to put the CPU (only the core, every other peripheral shall remain running) in sleep when there is nothing to do and be ready to resume as soon as an interrupt fires. In this way I could read the value of a timer (LPIT or FlexTimer) just before the wfi instruction and immediately after to get an estimate of the idle time. I'm not interested in any powersaving feature.
From what i read in the ARM documentation I should use the ARM sleep mode, but in the S32K reference manual there is no information about that. On the contrary it describes the STOP2 mode which also seems to be a good candidate for the job (core clock stopped, but almost everything else enabled).
What would be the best option for my pourposes?
For your purpose, the best option is, as you said, STOP2 because the bus clock remains active, but FTM (FlexTimer module) is OFF in the STOP modes.
The LPIT has full functionality in the STOP2, so, you can use it. However, the timers have some disadvantages.
The LPIT you can read only in the interrupt. The LPTM is only 16-bit and RTC is accurate when you have an external clock.
So, it depends on your application.
Also, I would like to recommend you to look at Table 38-4. Module operation in available power modes to see each module functionality in this mode.
Also, you can look at AN5425. There the STOP mode entry sequence can be seen.
I hope it helps.
Hi, Thanks for the answer.
No, sorry, I noticed that the FTM is required in my application and can't be stopped, so STOP2 is not applicable.
However from the application note AN5425, I understand that ARM Sleep mode is indeed available on the S32K (paragraph 2.1), but the document does not say what are the effects on other peripherals. Are they affected if I put the Core in Sleep?
I would like a clarification on that, please.
Thanks for the support,
The sleep mode which you are looking for is called "Wait mode" in the RM.
"Wait mode is not supported in this device. See Table 38-4. Module operation in available power modes for
details on available power modes."
Unfortunately, the S32K1xx device does not support WAIT, VLPW and low
If so then application note is incorrect, see paragraph 2.1
The reference manual too say something about it
even if it doesn't explain much more. I think the reference manual is not very clear about this.
Also where in the manual can I find a definition of Wait mode and its association with ARM sleep?
It isn't very clear as you said. I will report to the apps team that "sleep mode" should be clearly described in the RM.
We can see the translation between ARM CPU mode and MCU power modes in section 39.2 Modes of operation. So, sleep mode is not there.
Also, the filed which represent sleep/wait power mode on the S32K1xx is empty in the AN5425 in Figure 1. Power modes comparison.
At first, I would like to mention a few points from RM rev. 11.
Also, please, look at the section 38.8 Module operation in available power modes, 39.2 Modes of operation and Table 39-1. Power modes
Deep Sleep is mapped to STOP/VLPS.
188.8.131.52 VLPS/Stop mode entry sequence
Entry into a low-power stop mode (Stop, VLPS) is initiated by a CPU executing the WFI
instruction. After the instruction is executed, the following sequence occurs:
27.4.4 VLPR/VLPS mode entry
When entering VLPR/VLPS mode, the system clock should be SIRC. The FIRC, SOSC,
and SPLL must be disabled by software in RUN mode before making any mode
transition. Ensure that CMU is gated by its PCC.CGC before entering STOP/VLPS/CPO
PMC_REGSC[BIASEN] must be set to 1 when using VLP* modes.