How can the time for SPI transmission initiation be shortened?

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How can the time for SPI transmission initiation be shortened?

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Leon06
Contributor III

Hi all,

I have some questions about S32K148 SPI using.

The SPI2 configuration is

 

/* SPI Master Configurations */
spi_master_t spi2_MasterConfig0 =
{
    .baudRate      = 4000000U,
    .ssPolarity    = SPI_ACTIVE_LOW,
    .frameSize     = 8,
    .clockPhase    = READ_ON_EVEN_EDGE,
    .clockPolarity = SPI_ACTIVE_HIGH,
    .bitOrder      = SPI_TRANSFER_MSB_FIRST,
    .transferType  = SPI_USING_DMA,
    .rxDMAChannel  = 2U,
    .txDMAChannel  = 3U,
    .callback      = NULL,
    .callbackParam = NULL,
    .ssPin         = 1,
    .extension     = NULL,
    .isPcsContinuous = true,
    .isMasterDevicesDelayed = false,
};

 

I aim to control the time required for transmitting 24 bits of SPI data to be under 10 us. However, I am currently facing challenges in reducing the duration between the SPI command and the CS (Chip Select) pin going LOW.

Leon06_0-1705286593632.png

 

void StartTransfer_SPI2(void* u8_tx_buff, void* u8_rx_buff, void* u16_len)
{
    SPI_MasterTransfer(&spi2Instance, u8_tx_buff, u8_rx_buff, *(uint16_t*)u16_len);
}

 

Leon06_1-1705286912126.png

How could I reduce the P1 P0 time for waiting the SPI Starting.

 

Regards,

Leon

 

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danielmartynek
NXP TechSupport
NXP TechSupport

Hi @Leon06,

What drivers / version do you use?

Can you read the LPSPI_CCR[PCSSCK] register?

 

Thank you,

BR, Daniel

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Leon06
Contributor III

Hi Daniel,

 

I am not sure about the SDK version. The attachments are the LPSPI driver from SDK, please check.

And I read out the register (*(g_lpspiBase[2])).CCR = 0x00140000.

 

Regards,

Leon

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danielmartynek
NXP TechSupport
NXP TechSupport

Hi @Leon06,

 

CCR = 0x00140000, PCSSCK = 0x14

danielmartynek_0-1705393446140.png

Use this function to set a shorter delay:

danielmartynek_1-1705393525317.png

 

Regards,

Daniel

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Leon06
Contributor III

Hi Daniel,

I am sorry. I am asking for reducing P0 not P1. P0 is the time between SPI starting transmission intimation and before the CS being low.

Leon06_0-1705419194874.png

Leon

 

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danielmartynek
NXP TechSupport
NXP TechSupport

Hi @Leon06,

The delay is caused by the overhead of the application SW and the LPSPI SDK driver.

You can either increase the system clock frequency or reduce the amount of code between Sample and CS assertion, for example by using you own code to drive the LPSPI.

https://www.nxp.com/docs/en/application-note/AN5413.pdf

AN5413SW

https://www.nxp.com/webapp/Download?colCode=AN5413SW&docLang=en

 

Regards,

Daniel

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