FTM CPWM with Complimentary mode and Deadtime

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FTM CPWM with Complimentary mode and Deadtime

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sean_dvorscak
Contributor III

I am looking for more information on how the FTM Deadtime works in Center-Aligned PWM mode and with Complimentary mode set.

I am seeing some weird behavior on a scope where it seems like the n channel is receiving deadtime at the rising edge of the pulse but not the back end.  So it sets at the offset that is relative to CnV+Deadtime, but then clearing at CnV.  The n+1 channel seems to be adding deadtime at the falling edge of the pulse.  So it sets at CnV and then clears at CnV+Deadtime.

Is this normal behavior?  Are there any app notes that will give more details about this specific setting?  All the deadtime examples shown in app notes and reference manuals show it in Up counting only.

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sean_dvorscak
Contributor III

Hello @danielmartynek ,

I figured out my problem.

So the signals on the scope are not the FTM PWM outputs.  My HW is configured such that FTM n Ch's go through a quad input AND gate, and FTM n+1 Ch's go through a quad input NAND gate.

Looking at the differences between Figures 47-75 and 47-76, it seems the dead time is inserted on the rising edge only.

Since we are in complementary mode, the FTM Ch 3 is actually rising at 38.75, but the NAND gate is showing it as a falling edge.

Sorry for the confusion.

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danielmartynek
NXP TechSupport
NXP TechSupport

This is how it should look like, in the center-aligned mode, the deadtime is asserted before each rising edge.

danielmartynek_0-1674741384860.png

danielmartynek_1-1674741625074.png

Please double-check the polarity of the signals in the POL register.

 

Regards,

Daniel

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sean_dvorscak
Contributor III

Hello @danielmartynek ,

I figured out my problem.

So the signals on the scope are not the FTM PWM outputs.  My HW is configured such that FTM n Ch's go through a quad input AND gate, and FTM n+1 Ch's go through a quad input NAND gate.

Looking at the differences between Figures 47-75 and 47-76, it seems the dead time is inserted on the rising edge only.

Since we are in complementary mode, the FTM Ch 3 is actually rising at 38.75, but the NAND gate is showing it as a falling edge.

Sorry for the confusion.

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sean_dvorscak
Contributor III

Hi @danielmartynek ,

I am not able to share my entire project with you.

To give more detail, I have FTM3 running at 80MHz with Center Aligned PWM mode enabled.  The MOD value is set to 0x7D0, which gets me time period of 50us.

I took some screenshots to show you exactly what I am seeing.  For this example, I am setting the PWM for 50% duty cycle, and I have a deadtime of 1.25us.  I am scoping FTM3 Channels 2 and 3 which have COMP1, DTEN1, SYNCEN1, and FAULTEN1 all set to 1 in the COMBINE register.  I have INITRIGS coming out at CNT = 0.  The Pink channel on top is the INITRIG, the middle Green channel is the FTM3 Ch 3, and the bottom red channel is the FTM3 Ch 2 on the scope.

What I would expect is that both PWM channels would rise at 13.75us from the INITRIG, but as you can see below, on FTM3 Ch 3 sets at 12.5us, while Ch 2 sets at 13.75us:

50%_rising_HS--00000.jpg

50%_rising_LS--00000.jpg

 

I would have also expected both channels to clear at 37.5us.  However, FTM3 Ch 2 clears at 37.5us, and FTM3 Ch 3 clears at 38.75us:

50%_falling_HS--00000.jpg

50%_falling_LS--00000.jpg

 

Looking at the POL register shows that they're all 0 at the time of the capture.  Why is that the Ch 2 has the deadtime inserted at the rising edge, and Ch 3 has the deadtime inserted at the falling edge?

FTM3_Registers_1.PNG

FTM3_Registers_2.PNG

Ultimately what I am trying to do is have some deadtime asserted between the FTM3 Ch2 and Ch3 such that they are both center aligned, but Ch 3 sets 1.25us before Ch 2, and clears 1.25us after Ch 2.

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danielmartynek
NXP TechSupport
NXP TechSupport

Hi @sean_dvorscak,

I think this is related to the issue reported in your second post here:

https://community.nxp.com/t5/S32K/Understanding-FTM-CPWM/td-p/1586873

It would be good if you could share the project.

Which S32K1xx MCU do you use?

 

BR, Daniel

 

 

 

 

 

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