BCTU questuon about interrupt with 4 ADC sample

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

BCTU questuon about interrupt with 4 ADC sample

Jump to solution
887 Views
Zhougw
Contributor III

I am using S32K396 for motor control.
I need BCTU to tigger 4 ADC sample, ADC0-2 for current, ADC3 for DC voltage(Now the control board is designed linke this). The original trigger source is eFlexPWM.
In S32K396, ADC0-2 are connected with BCTU0, ADC3-7 are connected with BCTU1.
I need three current sampled in parallel, what interrupt should I use,BCTU0 interrupt,BCTU1 interrupt?
or I should use ADC2 to sample 1 current and DC voltage in serial?

note:
when interrupt is triggered, 4 sample should be all finished.
As I was told, I don't need DMA to transfer ADC data. DMA is used to transfer ADC data in demo code because they want to test DMA performance, it isn't necessary.

0 Kudos
1 Solution
830 Views
PetrS
NXP TechSupport
NXP TechSupport

Hi,

yes, parallel conversion should be finished at a same time, assuming clock and ADC sample timing setting is same on each ADCs. 
I can recommend to use FIFO as a result destination, then with using right FIFO watermark you will know all converted results are available in it.

BR, Petr

View solution in original post

0 Kudos
8 Replies
866 Views
PetrS
NXP TechSupport
NXP TechSupport

Hi,

it depends how BCTU triggers and conversion list are configured, but if there is just single trigger, then parallel conversion will happens normally and should be all finished at the same time. Then it does not matter what interrupt is selected. Anyway you should still check interrupt flags in interrupt to be sure result is ready in data registers or FIFOs.

BR, Petr

0 Kudos
843 Views
Zhougw
Contributor III
so you mean if ADC0-2 sampling started simultaneously( BCTU configure one channel for each group of ADC) , it would definitely finished at the same time?
In that condition, I only need to set ADC2 as the trigger source and don't need to judge if ADC0 and ADC1 finished or not in intterupt task, then my doubts are solved.
0 Kudos
831 Views
PetrS
NXP TechSupport
NXP TechSupport

Hi,

yes, parallel conversion should be finished at a same time, assuming clock and ADC sample timing setting is same on each ADCs. 
I can recommend to use FIFO as a result destination, then with using right FIFO watermark you will know all converted results are available in it.

BR, Petr

0 Kudos
805 Views
Zhougw
Contributor III
I was wondering if DMA and FIFO can achive the same effect.
use CL list for adc sample in BCTU0.

usage1: tigger interrupt when sampling of 3 current finished.
BCTU0_ADC_DMA: use DMA for currentW sampling as interrupt source.
BCTU0_ADC_FIFO: set watermark level=2

usage2: tigger interrupt when sampling of 3 current and DcVoltage finished.
BCTU0_ADC_DMA: use DMA for DcVoltage sampling as interrupt source.
BCTU0_ADC_FIFO: set watermark level=3.(use ADC0 to sampleDcVoltage)
0 Kudos
768 Views
PetrS
NXP TechSupport
NXP TechSupport

Hi,

I do not understand this question. Watermark specify how many stored results in FIFO trigger interrupt or DMA request. Then it should be read out in interrupt or by DMA.

BR, Petr

0 Kudos
765 Views
Zhougw
Contributor III
for example , I sample 3 phase current, and some other ADC signal. set watermark =2, after 3 phase current sampling finished, interrupt will generate,I read the result of 3 phase current. after 3 other adc signal sampling finished, interrupt will also generate. so the limit is water mark should be ≥ (the total num of ADC channel used)/2 -1。 for example, total adc signal is 8, water mark should be greter than 3, or there will be more than 1 interrupt.
0 Kudos
762 Views
PetrS
NXP TechSupport
NXP TechSupport

Hi,

if you have 8 ADC to be converted into same FIFO with watermark=2, then if you read 3 results from FIFO, the interrupt will be called twice.

BR, Petr

0 Kudos
724 Views
Zhougw
Contributor III
thank you, Petr.
0 Kudos