S32G2/VR5510 WATCHDOG

[Delishtm]

We are bringing up  S32G2 and its PMIC (VR5510) in our customized board. PMIC output rails are coming correctly. But we are seeing issues with PMIC reset. 

It looks like the internal watchdog of PMIC is resetting the PMIC in a specific interval of time and shutting down the power in a periodic fashion. To program the Processor we need the reset to be released. we have verified that during power up, VDDOTP is high for more than Debug mode entry filtering time. 

We have captured VDDOTP with PWRON and PMIC reset signals in scope. Scope shots are attached  for your reference. The naming of the scope images is like <capture number>_<channel name1>_<signal name>_<channel name 2>_<signal name>.

Our observations are

• Once the power is up, PMIC reset goes high. But after around 1 sec, PMIC reset is going low for 10ms. This repeats 5 times.
• After that power shuts off for around 4 sec.
• Again power comes up and the process repeats.

Can you help us here to resolve this issue? Our intention is to program S32G processor with our software code. But since power shuts off, we are not able to do that.

[Delishtm · Accepted solution]

@guoweisun 

Q1 ANS

PMIC P/N:MVR5510AMBAHES

Since the P/N is a preprogrammed IC we have not done any programming.

Q2 ANS

Our observation is the PMIC is not staying in debug mode and it's getting resetted.

Can you help us to resolve this issue?

[guoweisun]

Please set VR5510 in debug mode to check it can start up correctly.

---

The VR5510 provides a means of evaluating the device in Debug mode. Debug mode
allows users, via the I2C interface, to access the OTP register set, modify the registers,
and test device functions. During Debug mode all regulators remain off.
The VR5510 enters in Debug mode with the following sequence:
1. Apply VDDOTP pin > 5 V.
2. Apply VSUP1/2 > VSUP_UVH and PWRON1 > PWRON1VIH or PWRON2 >
PWRON2VIH.
3. The device now starts in Debug mode, ready for debugging or OTP programming.
4. Apply VDDOTP = 0 V to turn on the device with the modified configuration.

[Delishtm]

@guoweisun 

Thank you for the valuable support you have provided. Now by making sure the following sequence

"1. Apply VDDOTP pin > 5 V.
2. Apply VSUP1/2 > VSUP_UVH and PWRON1 > PWRON1VIH or PWRON2 >
PWRON2VIH."

We are able to enter the debug mode and the watchdog has been disabled.

I have one doubt remaining

Q) I saw this in the datasheet "During Debug mode all regulators remain off." As per my understanding In OTP mode, we will not get the voltage rails right? & in debug mode we will get the output rails? Is that right ?

[guoweisun]

Please see the completely flow chart of enter debug mode on datasheet page20,the regulators power up after DBG=0V:

[Delishtm]

@guoweisun At that state, the PMIC will be in Debug mode (Internal PMIC watchdog disabled) right?

[guoweisun]

In the above flow chart ,there is step named disable WD in the INIT phase,after set this no need WD refresh:

The watchdog window
can only be disabled during the INIT_FS phase. A watchdog disable takes effect when
INIT_FS closes.

[SBH]

Had queries on PMIC watchdog enable:

1) Is it also done in INIT_FS phase?

2) Whether INIT_FS phase can be entered during application initialization stage OR Is it restricted to be done only by bootloader during boot up?

We tried to configure PMIC watchdog from AUTOSAR side: Is it the right way? 

[guoweisun]

1：Does your VR5510 finish OTP?or what 's the full part number of VR5510?

2: Suggest to operate VR5510 in debug mode before debug the software.