Hello,
By default, when integrating the PFE driver into the `fsl-image-auto`, `s32g-pfe-bmu2-pool` and `s32g-pfe-rt-pool` are placed in SRAM.
I need to move them to DDR, but I have tried various configurations, and I cannot get the driver to work.
I cannot find the requirements for placing the buffers in DDR.
Could you please suggest a possible configuration?
Thank you.
reserved-memory {
pfe_reserved_bmu2: pfebufs@34000000 {
compatible = "nxp,s32g-pfe-bmu2-pool";
/* BMU2: 512 KB */
reg = <0 0x34000000 0 0x80000>;
no-map;
status = "okay";
};
pfe_reserved_rt: pfebufs@34080000 {
compatible = "nxp,s32g-pfe-rt-pool";
/* RT: 128 KB */
reg = <0 0x34080000 0 0x20000>;
no-map;
status = "okay";
};
pfe_reserved: pfebufs@83200000 {
compatible = "shared-dma-pool";
/* 4 MB - 128 KB */
reg = <0 0x83200000 0 0x3e0000>;
no-map;
status = "okay";
};
pfe_reserved_bdr: pfebufs@835e0000 {
compatible = "nxp,s32g-pfe-bdr-pool";
/* 128 KB */
reg = <0 0x835e0000 0 0x20000>;
status = "okay";
};
/* ends 0x83600000 */
};
Solved! Go to Solution.
Hi,
Thanks for your feedback. We understand that the following information is available:
"
Moved bmu2 to address 0x83600000 successfully. Actually only device tree should be modified.
1. chage device tree s32g.dtsi.
"
Please, let us know.
Hi,
Can you confirm which PFE-FW version you are working with? We also see the following information is provided under the LNX PFE Driver User Manual:
Also, the following requirements are provided:
Please, let us know.
Hello,
Thank you for your response.
We are currently using the `NXP S32G PFE Firmware version 1.8.0`.
Also, I'm seeking clarification regarding the requirement stating "the alignment must equal the size of the region for BMU2." Could you please elaborate on this requirement and provide examples to better understand its implementation?
Thank you.
Hi,
Thanks for your feedback. We understand that the following information is available:
"
Moved bmu2 to address 0x83600000 successfully. Actually only device tree should be modified.
1. chage device tree s32g.dtsi.
"
Please, let us know.
Hello,
After following the suggested steps,
From 4bfb3ededee92bbc8760ab11ea571d1bd2dcd940 Mon Sep 17 00:00:00 2001
From: xxxx xxxx xxxx xxxx
Date: Mon, 4 Mar 2024 14:30:02 +0100
Subject: [PATCH] Configure PFE system buffers exclusive regions
---
arch/arm64/boot/dts/freescale/s32g.dtsi | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/s32g.dtsi b/arch/arm64/boot/dts/freescale/s32g.dtsi
index 25adbf77244f..27f15683c05e 100644
--- a/arch/arm64/boot/dts/freescale/s32g.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g.dtsi
@@ -25,18 +25,18 @@ aliases {
};
reserved-memory {
- pfe_reserved_bmu2: pfebufs@34000000 {
+ pfe_reserved_bmu2: pfebufs@83600000 {
compatible = "nxp,s32g-pfe-bmu2-pool";
/* BMU2: 512 KB */
- reg = <0 0x34000000 0 0x80000>;
+ reg = <0 0x83600000 0 0x80000>;
no-map;
status = "okay";
};
- pfe_reserved_rt: pfebufs@34080000 {
+ pfe_reserved_rt: pfebufs@83680000 {
compatible = "nxp,s32g-pfe-rt-pool";
/* RT: 128 KB */
- reg = <0 0x34080000 0 0x20000>;
+ reg = <0 0x83680000 0 0x20000>;
no-map;
status = "okay";
};
--
2.43.2
The PFE driver is now functioning as expected.
m[ 8.526310] pfeng 46000000.pfe: TX clock on EMAC0 for interface sgmii installed
[ 8.526355] pfeng 46000000.pfe: RX clock on EMAC0 for interface sgmii installed
T[ 8.526415] pfeng 46000000.pfe: TX clock on EMAC1 for interface sgmii installed
im[ 8.526457] pfeng 46000000.pfe: RX clock on EMAC1 for interface sgmii installed
e[ 8.526531] pfeng 46000000.pfe: TX clock on EMAC2 for interface rgmii-id installed
S[ 8.526569] pfeng 46000000.pfe: RX clock on EMAC2 for interface rgmii-id installed
e[ 8.526588] pfeng 46000000.pfe: memory-region: nxp,s32g-pfe-bmu2-pool node missing
t[ 8.526593] pfeng 46000000.pfe: fall back to default pool allocation
8.526670] pfeng 46000000.pfe: assigned reserved memory node pfebufs@83680000
0[ 8.526756] pfeng 46000000.pfe: assigned reserved memory node pfebufs@83200000
m.[ 8.526793] pfeng 46000000.pfe: assigned reserved memory node pfebufs@835e0000
[ 8.531651] pfeng 46000000.pfe: Firmware: CLASS s32g_pfe_class.fw [45040 bytes]
[ 8.531674] pfeng 46000000.pfe: Firmware: UTIL s32g_pfe_util.fw [23252 bytes]
[ 8.531704] pfeng 46000000.pfe: PFE CBUS p0x46000000 mapped @ v0xffffffc00a000000 (0x1000000 bytes)
[ 8.531716] pfeng 46000000.pfe: Silicon S32G2
[ 8.532826] pfeng 46000000.pfe: PFE_ERRORS:Parity instance created
[ 8.532838] pfeng 46000000.pfe: PFE_ERRORS:Watchdog instance created
[ 8.532846] pfeng 46000000.pfe: BMU1 buffer base: p0xc0000000
[ 8.533044] pfeng 46000000.pfe: BMU2 buffer base: p0x83200000 (0x80000 bytes)
[ 8.534589] pfeng 46000000.pfe: register IRQ 77 by name 'PFE BMU IRQ'
root@s32g274ardb2:~# ip -c a
1: lo: <LOOPBACK,UP,LOWER_UP> mtu 65536 qdisc noqueue state UNKNOWN group default qlen 1000
link/loopback 00:00:00:00:00:00 brd 00:00:00:00:00:00
inet 127.0.0.1/8 scope host lo
valid_lft forever preferred_lft forever
inet6 ::1/128 scope host
valid_lft forever preferred_lft forever
2: can0: <NOARP,ECHO> mtu 16 qdisc noop state DOWN group default qlen 10
link/can
3: can1: <NOARP,ECHO> mtu 16 qdisc noop state DOWN group default qlen 10
link/can
4: sit0@NONE: <NOARP> mtu 1480 qdisc noop state DOWN group default qlen 1000
link/sit 0.0.0.0 brd 0.0.0.0
5: pfe0: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state UP group default qlen 1000
link/ether 00:04:9f:be:ef:00 brd ff:ff:ff:ff:ff:ff
inet 192.168.1.70/24 brd 192.168.1.255 scope global pfe0
valid_lft forever preferred_lft forever
inet6 fe80::204:9fff:febe:ef00/64 scope link
valid_lft forever preferred_lft forever
6: pfe1: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state UP group default qlen 1000
link/ether 00:04:9f:be:ef:01 brd ff:ff:ff:ff:ff:ff
inet6 fe80::204:9fff:febe:ef01/64 scope link
valid_lft forever preferred_lft forever
7: pfe2: <NO-CARRIER,BROADCAST,MULTICAST,UP> mtu 1500 qdisc mq state DOWN group default qlen 1000
link/ether 00:04:9f:be:ef:02 brd ff:ff:ff:ff:ff:ff
8: aux0: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state UP group default qlen 1000
link/ether 00:04:9f:be:ef:80 brd ff:ff:ff:ff:ff:ff
inet6 fe80::204:9fff:febe:ef80/64 scope link
valid_lft forever preferred_lft forever
9: hif3: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state UP group default qlen 1000
link/ether 00:04:9f:be:ef:f0 brd ff:ff:ff:ff:ff:ff
inet6 fe80::204:9fff:febe:eff0/64 scope link
valid_lft forever preferred_lft forever
Thank you sincerely for your assistance.
I also do the same but still my PFE is disable ,can you tell me what patch i need to add to enable PFE ,i am using s32g2 linuxbsp39.0 ,i want to enable pfe and i do changes and create patch but where i need to add that patch which .bb file please guide me ?