LPDDR4 Performance Analysis on S32G-VNP-EVB

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LPDDR4 Performance Analysis on S32G-VNP-EVB

Contributor II


Board: S32G-VNP-EVB

S/W: Diagnostic Software(SW32G2-DIAG-EAR-0.8.6.zip)

We are testing LPDDR4 performance tests.

As part of the test got below output:

DDRTest#6:DDR Performance Monitor Test - ddr_perf_mon_test - Started
Performance Numbers:
DRAM access duration for read throughput 5368709 us

Performance Monitor - Counter_2 Write Data Count 22823433
Performance Monitor - Counter_1 Read Data Count 15935937

DRAM read throughput by counter with burst size '7': 14 MBps
DRAM access duration for write throughput 5368709 us
DRAM write throughput by counter with burst size '7': 28 MBps

DRAM last read location: 0x63cca704
DRAM Total read locations in total duration: 15935937 Bytes
DRAM last write location: 0x67ea3bfc
DRAM Total write locations in total duration: 33197823 Bytes
DDRTest#6: ddr_perf_mon_test - Passed !!!


1. For running the test we are enabling the counter to 1, but how it is related to total time conducted on test, For calculation below formula is used (0xFFFFFFFF/80) in App ?

2. Performance Monitor - Counter_2 Write Data Count and DRAM Total write locations in total duration are not same in write scenario, but same in read case.

3. LPDDR4 theoretical bandwidth is 25.6GB/s, in the current test is displaying 14 MBps for write and 28 MBps 




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NXP TechSupport
NXP TechSupport

The ddr_perf_mon_test is provided with diagnostics application in order to enable performance monitor module and reference configurations for enabling counters & signals to be monitored in users/customers applications. This test could not be used for benchmarking or max DDR bandwidth observations. In my reference configurations, there is only one master (CM7 only) at one AXI port (AXI2/64-bit) for read/write which could not be a good case to stress the DDR system for bandwidth measurements and seems that is why you observed less performance with provided reference configurations.

In order to observe max bandwidth, user should load/stress all DDR controller AXI ports for read/write transactions. 

To observe DDR transactions performance using performance monitor module, the DDR performance monitor feature is implemented in Linux and provided with BSPs. Please refer Linux BSP release notes and user manual for usage.




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