How to boot all processors on the chip

[MateoSegura413]

Hello NXP team/community.

I feel like this question shouldn't come as a surprise to any of you, as there are plenty of posts like this one, or this one, which ask this same question: How do I boot ALL the cores of the S32G SoC.

Please do not tell me to go read the documentation. No offense, but it is extremely scattered and detailed in ways that are NOT useful at all for real development. Or at least not the parts that matter.

It says everywhere that you can boot either an M7 or A53 core and then boot the rest of the cores from it. BUT HOW? WHERE IS THE EXPLANATION/EXAMPLES OF HOW TO DO THIS?

Everybody in the community seems to be just as lost and frustrated about this process, which should be obvious. It is mind-blowing that you release a chip of this level of complexity with the kind of documentation and support that you offer.

THE IPCF EXAMPLE IS NOT ENOUGH! It doesn't explain why the u-boot commands are there, it has as modified linker file that is not the default when you create a new project, and it only boots 1 M7 core.

So I'm going to ask, kindly:

What is the process to boot all 3 real time clusters, as well as Linux on the A53 cores?

Can I do so from U-boot/Linux/RT core?

Where do I store the binaries for the RT cores?

Thanks in advance for not referring me to the documentation and answering with an actual helpful answer!

[asap]

just to update to this thread, there is a new AN13750 enabling multicore application published last month on nxp.com/s32g2 page.

[nxp19]

I would like some documentation on that topic, too.

I totaly agree the documenation is scattered around the website, with a lot of places you can not even save a bookmark of or link somebody else to it. Most of the time finding the right software package and documentation feels more like hunting easter eggs than anything else. And even if you found some place with the software you are looking for, it may be the wrong version. For some reasons a lot of downloads on the official website are out-of-date.

For most stuff you can reverse engineer what you need by samples and documentation fragments. But specially the boot process is quite a mystery wrapped in riddles. Some things are documented / intuitive:
- Running Linux on A53 with the Yocto image
- Running M7 cores bare-metal by debugger / sideload

But I need some example / documentation how to get the M7 cores booting and handling like CAN / SPI Connections while the A53 is running linux. So far i did only find the IPCF example and webinar for this module. - Which at least shows how to start the M7 by u-boot. But it does not give any explanation how that works. If you try the same commands with the UART example it utterly fails and prints garbage / crashes without error messages.

What I would need is a simple explanation what is needed to compile / package the software for the M7 cores and add them to the sdcard image via Yocto. (And yes, I had a look at the GoldVIP package but i does not help. The package need Tresos and a lot of other stuff I do not have / want to use)

[JetXiong]

Hi, Thanks very much for your feedback and contribution.  We have a plan to build a step-by-step user guide on how to boot the follow cores:

• M7-0,M7-1,M7-2, 
• A53, uboot/Linux

The guide will be based on following software release of "Bundle-4".  It will be available by early July depend on the bundle-4 final release date. 

• Integration platform – bootloader.
• RTD Non-AutoSAR driver  
• BSP32 – uboot/Linux
• A simple app running on 3 M7 core - “hello world”.

 Meanwhile,  we have sufficient documentation for customer to get started.

• Integration platform, we have a bootloader demo for M7 and A53 boot.
• We have software enablement guide on RDB2 web page for how to build IVT for flash/SD boot.

When you go through this demo/document, all you need is some customization to boot another M7 core.

• Bootloader modification .
• IVT modification

Would you mind to tell us more information about what OS and task you will run on these separate M7 core, how are you going to allocate the resource?  Thanks.

[BGauthier]

Hi JetXiong,

Did you come up with the plan you describe above?

If so, would you mind sharing the URL?

Here is my problem with the S32G-VNP-RDB2/S32G274A platform

• I tried all the baremetal M7 samples provided with the S32DS3.5 IDE such as Linflexd_Uart_Ip_Example_S32G274A_M7.
• When starting the M7 app with the debugger or from U-BOOT, I can see the M7 app output on the UART1. 
• But the CORTEX-A53 side (U-BOOT or Linux) hang.
• I tried IPCF example (M7 baremetal <->Linux BSP30.0) and it's working, nothing hang, I can see the M7 exchanging messages with the A53 Linux.
• What I want to do is to use the UART1 console from the M7 app without killng Linux or U-BOOT.
• As you might know, the IPCF M7 baremetal app is makefile based, I haven't found yet an easy way to add the UART SDK component without snowballing into a make/build nightmare.

BTW:

• I followed the guideline S32G-VNP-RDB2-SW-UG.pdf "S32G-VNP-RDB2 SOFTWARE ENABLEMENT GUIDE", the IVT section to create the .bin file.
• The IVT binary file doesn't seems to start, but the M7 binary created by the S32DS works but hanging the A53.

Thanks for your help,

Bruno

[StanleyShen]

Sorry to interrupt

Like many people, I am confused about this problem too.

Do you have such a guide like this?

[We have a plan to build a step-by-step user guide on how to boot the follow cores]

In addition 

[Would you mind to tell us more information about what OS and task you will run on these separate M7 core, how are you going to allocate the resource]

Just for me

Boot target - M7_0

Boot mode - QSPI

A53 side - BSP30(Actually, I have compiled it and started it in SD mode)

M7 side - No OS is required, just print "hello world" on UART1

S32G Design Studio 

windows program tool 

Thank you 

[BGauthier]

Hi Stanley,

Please find below the instructions to load/run an M7 application, located on the SD card, from U-BOOT.

Please notice the application example build from the S32DS IDE will run, but hand U-BOOT/A53/Linux.
While the IPCF M7 example won't (build from makefile)
I'm suspecting the SDK startup used by the S32DS IDE to be the culprit.

Thanks,
Bruno

• setenv xw_file IPCF_Example_S32G274A_M7_0.bin ##  IPCF_Example_S32G274A_M7_0.bin is located on your SD card, use fatls mmc 0:1 to confirm
• setenv xw_load_addr 0x34300000 ## refer to: S32G2RM.pdf, chap 3, use acroread, the section is an attachment to the pdf.
• setenv xw_load_firmware dcache off; mw.q ${xw_sram_address} 0x0 0x100000; fatload mmc 0:1 ${xw_load_addr} ${xw_file}; startm7 ${xw_start_addr}
• setenv xw_sram_address 0x34000000
• setenv xw_start_addr 0x34501000
• setenv bootcmd run ${xw_load_firmware}; ${bootcmd} ## optional
• saveenv
• run xw_load_firmware ## this will load/run IPCF_Example_S32G274A_M7_0 located on the SD card

After that, everytime you boot, your S32G target will:

1. the IPCF_Example_S32G274A_M7_0.bin will be copy from the SD card to sram
2. the IPCF_Example_S32G274A_M7_0.bin will executed oh the M7
3. the A53 will boot Linux

[StanleyShen]

Hi  Bruno

Thank you very much for teaching me how to make it.

From your description, I know how to start both A53 and M7 APP from SD-Card mode.

Also

I found the other way to confirm boot all processors, just refer to the attached file, 

I have confirm the IPCF communication completely.(QSPI mode)

If necessary, you can also refer to this document.

Thank you.

[StanleyShen]

Hi  Bruno

Thank you very much for teaching me how to make it.

From your description, I know how to start both A53 and M7 APP from SD-Card mode.

Also

I found the other way to confirm boot all processors, just refer to the attached file, 

I have confirm the IPCF communication completely.(QSPI mode)

If necessary, you can also refer to this document.

Thank you.

[jbirchy]

@JetXiongi s Bundle-4 released, and if so where would I find it because I don't see anything referred to as "Bundles" in my Software Products (I have access to S32G & GoldVIP).

If it is not released, might your NXP Autommotive FAEs have access to the step-by-step user guide to build Linux & the RTOSs and deploy them to the RDB2?

Thank you

  John (dedicated NXP automotive FAE @ Avnet)

[zhouwg]

Dear NXP Expert,

Thanks for your great efforts and the coming "bundle-4 final release" would be very helpful for S32G developers.

After study “Chapter 30:Boot" in the <<S32G2 Reference Manual>> and "HOWTO: Use IVT Tool To Create A Blob Image S32G274... - NXP Community"  and relevant posts in NXP community , could you help to clarify how to create a standalone FIP/FIT image(which could be used for boot the A53-0 core) manually?  This demo will be useful for daily CI(without S32 DS IDE) activities. Do you have any plan to add such demo to the "bundle-4 final release"?

Thanks.

Best Regards

[nxf45013]

Hi, 

Currently, the most comprehensive demo which covers your queries is the GoldVIP project.
In there, we use the Platform Integration Bootloader to boot the platform. Three binary images are involved in the boot process:

1. Image Vector Table + Bootloader (M7) + HSE, bundled together
2. M7 multicore Autosar Application (gateway application)
3. ARM Trusted Firmware (ATF)

The boot process for GoldVIP is the following: 

1. Preparation phase:
   • Deploy the GoldVIP SD CARD image using win32diskimager. 
   • Boot the board from SD and stop in u-boot prompt.
   • Run the following command: run write_goldvip_images and wait for the command to finish. This will write the images in the QSPI flash.
   • Set the board to boot from QSPI.
2. Pre-configuration phase:
   • Bootloader is booted by the BootRom
   • Bootloader creates a secure memory region and registers it in the HSE System image. The secure memory region is actually linked to the application bootloader. In other words, the bootloader signs its own image from flash.
   • The HSE system image is saved in flash.
3. Run phase:
   • Bootloader is booted by HSE using the Secure Memory region mentioned previously.
   • Bootloader copies the images for M7 (gateway application) and A53 (ATF) from Flash to RAM.
   • Bootloader starts the A53 core and jumps to the M7 application.
   • On A53, the A53_0 is started initially. The ATF will then boot the rest of the A53 cores.
   • On M7, the M7_1 core is started by the M7_0.

It is possible to start cores from the Bootloader, as this component can be configured using EB tresos. You can check the EB tresos workspaces offered as part of the GoldVIP installer.

Hope this clears it,
Vlad

[MateoSegura413]

Hello,

Although I appreciate the information, I have already tried this GoldVIP package. But there's one key component here you're missing:

These are binaries. Completely and entirely useless other than to prove the SoC works.

I cannot reproduce this with my own software. I cannot boot the Cortex M7_1 from M7_0 because there's no documentation on how to do this. I cannot boot all three M7s from A53, again, no information on how to do this.

I get that I have to have all these components (IVT, DCD, HSE, etc). I've read the documentation. This still does not explain and show how to boot everything.

As far as the GoldVIP goes, a lot of it assumes that the customer is using AUTOSAR/EB Tresos

Why do you prioritize support for this over your own tools (S32DS?)

[nxf45013]

Hi,

You can also find the configurations and the source code. Please check the GoldVIP developer guide for details on how to recreate the binaries. 

You shall be able to rebuild the binaries, if you follow the steps. 

GoldVIP includes the EB Autosar stack, which does not have support for S32DS.

Let me know if you have other questions.

LE: The M7_1 is started from the Mcu driver. Please check the tresos configuration for the Realtime application -> Mcu -> ModeSettingsConfig. The bootloader can also perform this initialization, but you would need to modify the tresos configurations. 

Vlad

[zhouwg]

I feel the same as you.Thanks.

I agree that booting all processors(MCU core + MPU core) at the same time should be naturally or obviously by the well organized documents and well organized SDK(similar to AOSP?).