Conflict: Unable to start M7 properly from U-boot

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Conflict: Unable to start M7 properly from U-boot

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yellapu_anishkh
Contributor IV

           Hi Team,

           I am using S32G RDB board, where i have to run M7 image from A53.

           Example:   Uart_Example_S32G399A_M7 from RTD 4.0.1

           BSP:BSP35

           Compiled uart example from S32DS and ran below commands from uboot.

           dcache off

           mw.q 0x34000000 0x0 0x600000

           fatload mmc 0:1 0x80000000 Uart_Example_S32G399A_M7.bin

          cp.q 0x80000000 0x34000000 0x600000

          startm7 0x34501000

          connected two serial cables UART0 for A53 and UART1 for M7. Once M7 image started, observed prints on UART1. But there is no response on A53.Suspected resource conflict. tried removing not required port config and clock configuration. Still issue remains same.

Please help me with the same.

Thank You,

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steklic_Ra
Contributor III

Hi, instead of this: mw.q 0x34000000 0x0 0x600000
try this: mw.q 0x34000000 0x0 0x100000, because this last number is not size, but number of quad blocks. 0x100000 will clear whole 8MB of SRAM, same logic you should apply to cp.q 0x80000000 0x34000000 0x600000, divide your binary size with 8, and that in hex should be last number. Currently you are clearing and writing memory that you should not access, and than you get kernel panic.

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yellapu_anishkh
Contributor IV

Hi Daniel,

Thank you for responding,

i have taken these commands from IPCF example. My intention is to run M7 and A53 images(Linux) from u-boot.

where i have ended up getting resource conflict. I have chosen UART over IPCF, where it is easy for me to visualize the output and understand the conflict.

 

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Daniel-Aguirre
NXP TechSupport
NXP TechSupport

Hi,

This procedure is only documented under the IPCF examples. If you want to load an M7 app through Linux, you need to take into account the ATF/u-boot being loaded into SRAM, as well as not initializing the shared modules multiple times (which we understand you are already doing).

We can recommend taking the IPCF linker and copying into the UART example or try to mirror the sections, but then again, we cannot confirm that the outcome will be as expected. We do apologize.

Please, let us know.

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yellapu_anishkh
Contributor IV

Hi Daniel,

Thanks for your input.

I have taken two paths.

Path1: boot m7 from uboot

Path2: boot m7 and a53 images from m7 (bootloader).

path1: i tried removing duplicate initialization and conflict, which is endless.

so i will stick to path2, where i took Integration_Reference_Examples_S32G3_2023_02 example and disabled secure boot as my intention is to boot image(ATF) with bootloader without security.

initial issue was SMR issue, so i have removed all fragments and selected just ATF.

I am able to set SMR to zero, by creating new entries in the tool.

Software config: To boot ATF from bootloader on A53.

Hardware: RDB3

Faced issue with XRDC because of memory restriction, disabled XRDC by removed rm_init().

Able to copy ATF from QSPI to SRAM address. Facing issue when jumping to ATF image.

ATF changes:

  • Alignment change is already there, as BSP35 image(fip.bin) is used.
  • BL2_BASE                := 0x34300000
  • Reset handler for bl2 is at 0x343001CC (With this code is not jumping to reset handler address, because of which ATF is not started)
  • Another iteration with reset handler at BL2_BASE, observation remains same.

Attached binaries for your reference.

Thank you for the support.

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Daniel-Aguirre
NXP TechSupport
NXP TechSupport

Hi,

Thanks for your feedback.

Have you look into the AN13750? It is available under the S32G2 product page (link: S32G2 Safe and Secure Vehicle Network Processor | NXP Semiconductors) which provides a configuration example for both M7 and A53 boot from NXP provided Bootloader.

It is explained with S32G2, but the general idea is provided.

As for the ATF, how are you moving the Base address?

Please, let us know.

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yellapu_anishkh
Contributor IV

Hi,

Thank you for the input.

I am able to progress in approach2. after successfully starting M7 app from uboot, when i boot to Linux it is crashing.

I have modified linker script as attached to avoid conflict with SRAM memory, still issue persists.

Kernel issue:

Starting kernel ...

[ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
[ 0.000000] Linux version 5.10.145-rt74+g1594b25154a2 (oe-user@oe-host) (aarc h64-fsl-linux-gcc (GCC) 10.2.0, GNU ld (GNU Binutils) 2.35.1) #1 SMP PREEMPT Tue Nov 29 10:33:39 UTC 2022
[ 0.000000] Anish::setup_arch
[ 0.000000] Anish:: Inside setup_arch init_mm.start_code=(____ptrval____) init_mm.end_code=(____ptrval____) init_mm.end_data=(____ptrval____) init_mm.brk=(____ptrval____)
[ 0.000000] Anish::1..........
[ 0.000000] Anish::2..........
[ 0.000000] Anish::3..........
[ 0.000000] Machine model: NXP S32G399A-RDB3
[ 0.000000] Anish::4...........
[ 0.000000] earlycon: linflex0 at MMIO 0x00000000401c8000 (options '115200n8' )
[ 0.000000] printk: bootconsole [linflex0] enabled
[ 0.000000] Anish::5...........
[ 0.000000] SError Interrupt on CPU0, code 0xbf000000 -- SError
[ 0.000000] CPU: 0 PID: 0 Comm: swapper Not tainted 5.10.145-rt74+g1594b25154 a2 #1
[ 0.000000] Hardware name: NXP S32G399A-RDB3 (DT)
[ 0.000000] pstate: 40000085 (nZcv daIf -PAN -UAO -TCO BTYPE=--)
[ 0.000000] pc : setup_arch+0x1c8/0x5fc
[ 0.000000] lr : setup_arch+0x1c0/0x5fc
[ 0.000000] sp : ffffffc010ca3ef0
[ 0.000000] x29: ffffffc010ca3ef0 x28: 0000000080b50018
[ 0.000000] x27: 00000000ffaa27f8 x26: 0000000000000000
[ 0.000000] x25: 00000000ffb3a508 x24: 00000000ffe067c8
[ 0.000000] x23: ffffffc010000000 x22: ffffffc010d44000
[ 0.000000] x21: ffffffc010cae380 x20: fffffffefe600094
[ 0.000000] x19: ffffffc010cf71d8 x18: 0000000000000030
[ 0.000000] x17: 0000000000001800 x16: 0000000000000000
[ 0.000000] x15: ffffffc010cae7e8 x14: ffffffffffffffff
[ 0.000000] x13: ffffffc090ca3b57 x12: ffffffc010ca3b64
[ 0.000000] x11: ffffffc010cb89e8 x10: ffffffc010ce4728
[ 0.000000] x9 : ffffffffffff0328 x8 : ffffffc010ca3a90
[ 0.000000] x7 : ffffffc010ce4620 x6 : ffffffc010d07ec7
[ 0.000000] x5 : 00000000fffffffe x4 : 0000000000000100
[ 0.000000] x3 : ffffffc010cb8588 x2 : 0000000000000000
[ 0.000000] x1 : 0000000000000000 x0 : 0000000000000080
[ 0.000000] Kernel panic - not syncing:
[ 0.000000] Asynchronous SError Interrupt
[ 0.000000] ---[ end Kernel panic - not syncing: Asynchronous SError Interrup

 

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Daniel-Aguirre
NXP TechSupport
NXP TechSupport

Hi,

Have you tried using the provided linker under the IPCF examples?

Please, let us know.

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yellapu_anishkh
Contributor IV

Hi,

I have directly used IPCF linker file and compiled UART example.

/*******************************************************************************
* GCC linker script for S32G3xx shared memory sample application
*
* Copyright 2021-2022 NXP
*
******************************************************************************/

HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x00003000;

ENTRY(Reset_Handler)

MEMORY
{
int_itcm : ORIGIN = 0x00000000, LENGTH = 0x00000000 /* 0KB - Not Supported */
int_dtcm : ORIGIN = 0x20000000, LENGTH = 0x00010000 /* 64K */
int_sram_shareable : ORIGIN = 0x22C00000, LENGTH = 0x00004000 /* 16KB */

SharedRAM (RW) : ORIGIN = 0x34000000, LENGTH = 0x00300000 /* 3MB */

int_sram : ORIGIN = 0x34300000, LENGTH = 0x00100000 /* 1MB */
int_sram_stack_c0 : ORIGIN = 0x34400000, LENGTH = 0x00002000 /* 8KB */
int_sram_stack_c1 : ORIGIN = 0x34402000, LENGTH = 0x00002000 /* 8KB */
int_sram_stack_c2 : ORIGIN = 0x34404000, LENGTH = 0x00002000 /* 8KB */
int_sram_stack_c3 : ORIGIN = 0x34406000, LENGTH = 0x00002000 /* 8KB */
int_sram_no_cacheable : ORIGIN = 0x34500000, LENGTH = 0x00100000 /* 1MB, needs to include int_results */
ram_rsvd2 : ORIGIN = 0x34600000, LENGTH = 0x0 /* End of SRAM */

LLCE_CAN_SHAREDMEMORY : ORIGIN = 0x43800000 LENGTH = 0x3C800
LLCE_LIN_SHAREDMEMORY : ORIGIN = 0x4383C800 LENGTH = 0xa0
LLCE_BOOT_END : ORIGIN = 0x4383C8A0 LENGTH = 0x50
LLCE_MEAS_SHAREDMEMORY : ORIGIN = 0x4384FFDF LENGTH = 0x20
}


SECTIONS
{

.sram :
{
. = ALIGN(4);
KEEP(*(.core_loop))
. = ALIGN(4);
*(.startup)
. = ALIGN(4);
*(.text.startup)
. = ALIGN(4);
*(.text)
*(.text*)
. = ALIGN(4);
*(.mcal_text)
. = ALIGN(4);
KEEP(*(.init))
. = ALIGN(4);
KEEP(*(.fini))

. = ALIGN(4);
*(.rodata)
*(.rodata*)
. = ALIGN(4);
*(.mcal_const_cfg)
. = ALIGN(4);
*(.mcal_const)
. = ALIGN(4);
__init_table = .;
KEEP(*(.init_table))
. = ALIGN(4);
__zero_table = .;
KEEP(*(.zero_table))

. = ALIGN(4);
*(.acfls_code_rom)
. = ALIGN(4);
*(.aceep_code_rom)
. = ALIGN(4);
*(.acmcu_code_rom)
. = ALIGN(4);
*(.ramcode)
. = ALIGN(4);
*(.data)
*(.data*)
. = ALIGN(4);
*(.mcal_data)
. = ALIGN(16);
__sram_bss_start = .;
*(.bss)
*(.bss*)
. = ALIGN(16);
*(.mcal_bss)
. = ALIGN(4);
__sram_bss_end = .;
} > int_sram

. = ALIGN(4);
__sram_shareable_rom = .;


.non_cacheable :
{
. = ALIGN(4);
KEEP(*(.int_results))
. += 0x100;
. = ALIGN(4096);
__interrupts_ram_start = .;
KEEP(*(.intc_vector))
. = ALIGN(4);
__interrupts_ram_end = .;
. = ALIGN(16);
__non_cacheable_bss_start = .;
*(.mcal_bss_no_cacheable)
. = ALIGN(4);
__non_cacheable_bss_end = .;
. = ALIGN(4);
*(.mcal_data_no_cacheable)
. = ALIGN(4);
*(.mcal_const_no_cacheable)
HSE_LOOP_ADDR = .;
LONG(0x0);
. = ALIGN(0x40000);
KEEP(*(.pfe_bmu_mem))
. = ALIGN(4);
KEEP(*(.pfe_bd_mem))
. = ALIGN(4);
KEEP(*(.pfe_buf_mem))
} > int_sram_no_cacheable
/* heap section */
.heap (NOLOAD):
{
. += ALIGN(4);
_end = .;
end = .;
_heap_start = .;
. += HEAP_SIZE;
_heap_end = .;
} > int_sram_no_cacheable

.llce_boot_end (NOLOAD) :
{
/* ------------------------------------ llce_boot_end sections ------------------------------------ */
. = ALIGN(0x4);
*(.llce_boot_end)
} > LLCE_BOOT_END

.can_43_llce_sharedmemory (NOLOAD) :
{
/* ------------------------------------ can_43_llce_sharedmemory sections ------------------------------------ */
. = ALIGN(0x4);
*(.can_43_llce_sharedmemory)
} > LLCE_CAN_SHAREDMEMORY

.lin_43_llce_sharedmemory (NOLOAD) :
{
/* ------------------------------------ lin_43_llce_sharedmemory sections ------------------------------------ */
. = ALIGN(0x4);
*(.lin_43_llce_sharedmemory)
} > LLCE_LIN_SHAREDMEMORY

.llce_meas_sharedmemory (NOLOAD) :
{
/* ------------------------------------ llce_meas_sharedmemory sections ------------------------------------ */
. = ALIGN(0x4);
*(.llce_meas_sharedmemory)
} > LLCE_MEAS_SHAREDMEMORY

.shareable_ram_bss (NOLOAD):
{
. = ALIGN(16);
__shareable_bss_start = .;
KEEP(*(.mcal_shared_bss))
. = ALIGN(4);
__shareable_bss_end = .;
} > int_sram_shareable

.shareable_ram_data : AT(__sram_shareable_rom)
{
. = ALIGN(16);
__shareable_data_start = .;
KEEP(*(.mcal_shared_data))
. = ALIGN(4);
__shareable_data_end = .;
} > int_sram_shareable

__sram_shareable_rom_end = __sram_shareable_rom + (__shareable_data_end - __shareable_data_start);

__Stack_end_c0 = ORIGIN(int_sram_stack_c0);
__Stack_start_c0 = ORIGIN(int_sram_stack_c0) + LENGTH(int_sram_stack_c0);
__Stack_end_c1 = ORIGIN(int_sram_stack_c1);
__Stack_start_c1 = ORIGIN(int_sram_stack_c1) + LENGTH(int_sram_stack_c1);
__Stack_end_c2 = ORIGIN(int_sram_stack_c2);
__Stack_start_c2 = ORIGIN(int_sram_stack_c2) + LENGTH(int_sram_stack_c2);
__Stack_end_c3 = ORIGIN(int_sram_stack_c3);
__Stack_start_c3 = ORIGIN(int_sram_stack_c3) + LENGTH(int_sram_stack_c3);

__INT_SRAM_START = ORIGIN(int_sram);
__INT_SRAM_END = ORIGIN(ram_rsvd2);

__INT_ITCM_START = ORIGIN(int_itcm);
__INT_ITCM_END = ORIGIN(int_itcm) + LENGTH(int_itcm);

__INT_DTCM_START = ORIGIN(int_dtcm);
__INT_DTCM_END = ORIGIN(int_dtcm) + LENGTH(int_dtcm);

__RAM_SHAREABLE_START = ORIGIN(int_sram_shareable);
__RAM_SHAREABLE_END = ORIGIN(int_sram_shareable) + LENGTH(int_sram_shareable) - 1;
__ROM_SHAREABLE_START = __sram_shareable_rom;
__ROM_SHAREABLE_END = __sram_shareable_rom_end;
__RAM_NO_CACHEABLE_START = ORIGIN(int_sram_no_cacheable);
__RAM_NO_CACHEABLE_END = ORIGIN(int_sram_no_cacheable) + LENGTH(int_sram_no_cacheable) - 1;
__ROM_NO_CACHEABLE_START = 0;
__ROM_NO_CACHEABLE_END = 0;
__RAM_CACHEABLE_START = ORIGIN(int_sram);
__RAM_CACHEABLE_END = ORIGIN(int_sram) + LENGTH(int_sram) - 1;
__ROM_CACHEABLE_START = 0;
__ROM_CACHEABLE_END = 0;

__BSS_SRAM_START = __sram_bss_start;
__BSS_SRAM_END = __sram_bss_end;
__BSS_SRAM_SIZE = __sram_bss_end - __sram_bss_start;

__BSS_SRAM_NC_START = __non_cacheable_bss_start;
__BSS_SRAM_NC_SIZE = __non_cacheable_bss_end - __non_cacheable_bss_start;
__BSS_SRAM_NC_END = __non_cacheable_bss_end;

__BSS_SRAM_SH_START = __shareable_bss_start;
__BSS_SRAM_SH_SIZE = __shareable_bss_end - __shareable_bss_start;
__BSS_SRAM_SH_END = __shareable_bss_end;

__RAM_INTERRUPT_START = __interrupts_ram_start;
__ROM_INTERRUPT_START = 0;
__ROM_INTERRUPT_END = 0;

__INIT_TABLE = __init_table;
__ZERO_TABLE = __zero_table;

__RAM_INIT = 0;
__ITCM_INIT = 0;
__DTCM_INIT = 1;
/* Discard boot header in RAM */
/DISCARD/ : { *(.boot_header) }

}

 

 

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Daniel-Aguirre
NXP TechSupport
NXP TechSupport

Hi,

Thanks for your feedback. With this are you still getting the same outcome?

Please, let us know.

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yellapu_anishkh
Contributor IV

Hi,

Thank you for the input. with this change Linux is starting.

However there is still some conflict with sdcard, when M7 binary started. I am suspecting interrupt conflict.

currently debugging the same.

#################Log###################################

[ 280.590891] mmc0: Timeout waiting for hardware cmd interrupt.
[ 280.590909] mmc0: sdhci: ============ SDHCI REGISTER DUMP ===========
[ 280.590915] mmc0: sdhci: Sys addr: 0x00000000 | Version: 0x00000002
[ 280.590921] mmc0: sdhci: Blk size: 0x00000200 | Blk cnt: 0x00000001
[ 280.590926] mmc0: sdhci: Argument: 0x00000000 | Trn mode: 0x00000000
[ 280.590931] mmc0: sdhci: Present: 0x01fd8009 | Host ctl: 0x00000001
[ 280.590936] mmc0: sdhci: Power: 0x00000000 | Blk gap: 0x00000080
[ 280.590940] mmc0: sdhci: Wake-up: 0x00000008 | Clock: 0x000040a7
[ 280.590945] mmc0: sdhci: Timeout: 0x0000000f | Int stat: 0x00018000
[ 280.590949] mmc0: sdhci: Int enab: 0x007f1003 | Sig enab: 0x007f1003
[ 280.590954] mmc0: sdhci: ACmd stat: 0x00000000 | Slot int: 0x00000502
[ 280.590958] mmc0: sdhci: Caps: 0x07eb0000 | Caps_1: 0x8000b407
[ 280.590963] mmc0: sdhci: Cmd: 0x00000502 | Max curr: 0x00ffffff
[ 280.590967] mmc0: sdhci: Resp[0]: 0x000001aa | Resp[1]: 0x00edc87f
[ 280.590972] mmc0: sdhci: Resp[2]: 0x325b5900 | Resp[3]: 0x00000900
[ 280.590977] mmc0: sdhci: Host ctl2: 0x00000000
[ 280.590981] mmc0: sdhci: ADMA Err: 0x00000000 | ADMA Ptr: 0x00000000
[ 280.590986] mmc0: sdhci-esdhc-imx: ========= ESDHC IMX DEBUG STATUS DUMP =========
[ 280.590990] mmc0: sdhci-esdhc-imx: cmd debug status: 0x2100
[ 280.590995] mmc0: sdhci-esdhc-imx: data debug status: 0x2200
[ 280.590999] mmc0: sdhci-esdhc-imx: trans debug status: 0x2300
[ 280.591003] mmc0: sdhci-esdhc-imx: dma debug status: 0x2400
[ 280.591007] mmc0: sdhci-esdhc-imx: adma debug status: 0x2500
[ 280.591012] mmc0: sdhci-esdhc-imx: fifo debug status: 0x2680
[ 280.591016] mmc0: sdhci-esdhc-imx: async fifo debug status: 0x2750
[ 280.591020] mmc0: sdhci: ============================================
[ 280.996672] EXT4-fs error: 1738 callbacks suppressed
[ 280.996691] EXT4-fs error (device mmcblk0p2): __ext4_find_entry:1580: inode #1247: comm launch_script.s: reading directory lblock 0
[ 280.996723] EXT4-fs error (device mmcblk0p2): __ext4_find_entry:1580: inode #1247: comm launch_script.s: reading directory lblock 0
[ 280.996752] EXT4-fs warning: 3594 callbacks suppressed
[ 280.996756] EXT4-fs warning (device mmcblk0p2): dx_probe:792: inode #2964: lblock 0: comm launch_script.s: error -5 reading directory block
[ 280.996782] EXT4-fs warning (device mmcblk0p2): dx_probe:792: inode #1248: lblock 0: comm launch_script.s: error -5 reading directory block
[ 280.996807] EXT4-fs warning (device mmcblk0p2): dx_probe:792: inode #1167: lblock 0: comm launch_script.s: error -5 reading directory block
[ 280.996834] EXT4-fs warning (device mmcblk0p2): dx_probe:792: inode #12: lblock 0: comm launch_script.s: error -5 reading directory block
[ 281.004116] EXT4-fs error (device mmcblk0p2): __ext4_find_entry:1580: inode #1247: comm launch_script.s: reading directory lblock 0
[ 281.004163] EXT4-fs error (device mmcblk0p2): __ext4_find_entry:1580: inode #1247: comm launch_script.s: reading directory lblock 0
[ 281.004190] EXT4-fs warning (device mmcblk0p2): dx_probe:792: inode #2964: lblock 0: comm launch_script.s: error -5 reading directory block
[ 281.004216] EXT4-fs warning (device mmcblk0p2): dx_probe:792: inode #1248: lblock 0: comm launch_script.s: error -5 reading directory block
[ 281.004240] EXT4-fs warning (device mmcblk0p2): dx_probe:792: inode #1167: lblock 0: comm launch_script.s: error -5 reading directory block
[ 281.004264] EXT4-fs warning (device mmcblk0p2): dx_probe:792: inode #12: lblock 0: comm launch_script.s: error -5 reading directory block
[ 281.008854] EXT4-fs error (device mmcblk0p2): __ext4_find_entry:1580: inode #1247: comm launch_script.s: reading directory lblock 0
[ 281.008897] EXT4-fs error (device mmcblk0p2): __ext4_find_entry:1580: inode #1247: comm launch_script.s: reading directory lblock 0
[ 281.008925] EXT4-fs warning (device mmcblk0p2): dx_probe:792: inode #2964: lblock 0: comm launch_script.s: error -5 reading directory block
[ 281.008950] EXT4-fs warning (device mmcblk0p2): dx_probe:792: inode #1248: lblock 0: comm launch_script.s: error -5 reading directory block
[ 281.017326] EXT4-fs error (device mmcblk0p2): __ext4_find_entry:1580: inode #1247: comm launch_script.s: reading directory lblock 0
[ 281.017368] EXT4-fs error (device mmcblk0p2): __ext4_find_entry:1580: inode #1247: comm launch_script.s: reading directory lblock 0
[ 281.019032] EXT4-fs error (device mmcblk0p2): __ext4_find_entry:1580: inode #1247: comm launch_script.s: reading directory lblock 0
[ 281.019072] EXT4-fs error (device mmcblk0p2): __ext4_find_entry:1580: inode #1247: comm launch_script.s: reading directory lblock 0

##############################################################

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yellapu_anishkh
Contributor IV

Hi,

After disabling unnecassary interrupts. i am able to resolve the issue.

Thank You.

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Daniel-Aguirre
NXP TechSupport
NXP TechSupport

Hi,

Good to know you got it working.

Have a great day.

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Daniel-Aguirre
NXP TechSupport
NXP TechSupport

Hi,

Where are you getting these commands from? We are not seeing any documentation that uses these commands for UART example and M7 booting from Linux.

The only application which uses Linux to boot the M7 core is the IPCF examples, but there is no additional documentation on implementing it on a different example.

Please, let us know.

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