I'm sorry for such late answer.
Requirements for this PWM generator changed a lot during this time. It stopped at 0,01-900[Hz]. This could be achievable with FTM with changing base CLKs for the FTM module. Unfortunately we had to use it for different thing and the rest of module where occupied.
I've decided to use LPIT timer (with 2 independent channels) and do a bit-banging software implementation.
It do a good job for low frequencies. I'm aware of that it will still burn a lot of CPU cycles, but have no idea of any other solution that would fit the requirements and it's better than just polling in main loop, which in our project need to have 2ms window.
FlexIO won't do the job here, because not every pin can make use of that.
Any way thank you for help.
Any suggestions will still be appreciated.
Supposing that 1 clock tick takes 0.00001s (I think this is possible only if you are using external clock source) the maximum value which can be measured by FTM timer is 0.65s due to 16 bit counter.
Taking into count that you are using relative large periods can you try to have a software implementation of the PWM?