Hi,
Specifying the input levels as 65% and 35% of VDD tells the user that by the time a rising voltage reaches 65% of VDD or above, it will be recognized as a logic-high level.
When a voltage falls to 35% of VDD or below, it will be recognized as a logic-low level. Voltages between these levels are generally undefined because it is not possible to predict which logic level the MCU will interpret.
Measuring one sample on the bench showed port A0 changed from 0 to 1 when the voltage exceeded 2.582 V with respect to ground.
Port A0 changed from 1 to 0 when the voltage was equal or less than 2.440 V. This shows a small hysteresis of 2.582 – 2.440 = 0.142 V (or 142 mV).
This is for one sample at 5.0 Vdc and room temperature of approximately 75°F (or 24°C). See figure below:
Note that automated test equipment often measures rise and fall times in terms of percent of VDD.
For example, on a common oscilloscope, the rise time is measured as the time a signal takes to move from 10% to 90% or 20% to 80% of VDD. This is not to be confused with the logic recognition levels in the previous paragraph.
[the above information is taken from the appnote AN2324 Input/Output (I/O) Pin Drivers on HCS12 Family MCUs]
Regards,
iggi
