period variation problem

[vinay]

Hi ALL,
                  I am working on a STARTER KIT demo board of softecmicro. The working IC is S12XDP512MAG and codewarrior 4.5 platform. i am just measuring the period between two pulses by using capture method. i give square pulses by signal generator to my port pin PIP2. every thing is working fine ie the period i am getting is exactlly what i want in normal debug mode as well as running mode.

                       but as i made my own small general perpose PCB board for this application. and i run the same program on my board i cant get exactly period between two pulses what i want and what i get from demo board of starter kit!.i get something variation from my cature value.

                      suppose i get capture value from demo board of staretr kit is 5000 (which i want and it is expected value also) it is totally OK. but same procedure i follow with my board sometime i get 5004.4998 sometimes 4999 and 5002.i get confuse where i am going to rong. is it my hardware going to be rong?. but i check all hardware it seem to be OK.

                      expect your valuable advice.

vinayak

[BasePointer]

Hi,

Your variation is 5 at 5000, that means 5/5000 = %0.1

Look at Jitter parameters in PLL Characteristics section in your device datasheet.

Variation of measured values is seen normal to me.

Regards,

BP.

Message Edited by BasePointer on 2007-12-14 10:57 AM

[kef]

From what you say it sounds like oscilator problem. Did you verify bus frequency and its stability. You may check it on ECLK pin. To get ECLK enabled, either clear NECLK bit from software or connect to the target with your BDM debugger, it should activate NECLK be default.

[vinay]

Thanks for reply,

                              May be u r right. i use the resonator of 4 MHz as a sourse clock and using PLL i made bus clock  20 MHz. after checkinmg  ECLK pin  some frequency distortion is there, it is not sinusoidal ,is it problem of resonator or frequency stability problem?? how can i remove it,will you please tell me?

Thanks

vinayak

[bigmac]

Hello Vinayak,

Your symptoms seem to suggest that the PLL loop may be unstable.  Have you closely followed the layout recommendations given in Appendix C of the data sheet?

The bypass capacitor between VddPLL and VssPLL connections is likely to be critical to stable operation.  Are you using the recommended capacitor type, and are the trace lengths between the pins and the capacitor kept very short?  The loop filter components connected to the XFC pin might also be checked.  Their return path to VddPLL should be very direct to minimize any possibility of noise pickup.  The presence of noise, at this point, will potentially frequency modulate the output of the PLL.

Regards,

Mac