Hi All,
Using 2 MM9z1_638 controller for SPI master and SPI slave.
In datasheet it mentioned as when it configured as Master---->Clock should be bus clock/2
when it configured as Slave---->Clock should be bus clock/4
So i decided to keep bus clock /4;
I am using bus clock as 28Mhz.
am using SPI to ensure both controllers are running on same time.
Initially mater will send character 'R'.Slave will reply with 'R'.
Then both will start executing there code.
To verify sync,I enabled 500ms timer. Every 500ms tone counter will increment both sided.
For every one sec master will ask counter value of slave and also stores its count value.If both counter are same then both are in sync.
But problem is
in master = 2,4,6,8,...
from slave =0,0,2,4
Initially two bytes getting 0.
Then i decided to send some dummy data from slave to master whenever interrupt hits.In this condition am getting proper value.
also i checked both are running on same speed.
Please let me know the problem.
Thanks,
Pavan
Hi,
Could you attach the debugger to the slave and check the state of the MCU?
The data that the slave returns must be prepared before the the master reads them.
The slave counter can be already 2 but if the SPI data register contains 0, it will return 0 during the transfer.
Do you monitor the SPI bus with an oscilloscope or a logic analyzer?
Regards,
Daniel
Hi Daniel,
Thank you for the information.
I will add some more point.yes am using oscilloscope to check values.Here also able to see zero.
Could you explain more on this line
"The data that the slave returns must be prepared before the the master reads them."
Thanks
Please find the code for SPI. I am using controller MM9Z1_639 NXP
Void Init(void) {
/* SPICR1 register configuration */
SPICR1_SPE = 1U;
SPICR1_LSBFE = 0U;
SPICR1_CPHA = 1U;
SPICR1_CPOL = 0U;
#ifdef MICRO1
SPICR1_MSTR = 1U;
SPICR1_SSOE = 0U;
SPICR1_SPIE = 0U;
SPICR1_SPTIE = 0U;
#endif
#ifdef MICRO2
SPICR1_MSTR = 0U;
SPICR1_SSOE = 0U;
SPICR1_SPIE = 1U;
SPICR1_SPTIE = 1U;
#endif /*SPICR2 register configuration */
SPICR2_XFRW = 0U; /* 8 bit data transfer */
SPICR2_SPC0 = 0U;
SPICR2_BIDIROE = 0U;
#ifdef MICRO1
SPICR2_MODFEN = 0U;
SPICR2_SPISWAI = 1U;
#endif
#ifdef MICRO1
SPICR2_MODFEN = 0U;
#endif
/*SPIBR configuration */
SPIBR = 0x01;
T_UBYTE Spi_ASample_Tx_Buf_Index = 0;
T_FLAG Spi_ASample_Sync_data; T_UBYTE Rx_Count = 0;
static T_UBYTE counter =0x03; static T_UBYTE call =0x00;
static T_UBYTE status_timer =0; v
oid ISR_FCT Spi_ASample_ISR(void) {
#ifdef MICRO2 if (SPISR_SPTEF) { (void)bspi_GetRxData();
if(status_timer==1)
{ SPIDRL=ADC_sync_time(); }
} #endif
}
void start_ADC_Sync_time()
{ if(status_timer>0)
{ call=(call+1); } }
T_UBYTE ADC_sync_time(void) { return call; }
void set_flag(void) { status_timer=1; }
Hi,
Sorry for the delay.
I just wanted to say that the SPIDR of the slave must be written before the master starts the transfer. It seems like it returns 0 because there are no data in the SPIDR of the slave during the first two transfers.
Regards,
Daniel