Yes, you are correct - the slave send data must be written to the SPI send buffer prior to the next interrogation by the master. So, when the slave SPI send buffer empties, the next send byte would be written, ready for a further transaction.
In many cases, this process for the slave is best handled within an ISR for the SPI, depending on the amount of data to be sent by the slave. Using a FIFO buffer would allow the ISR to automatically load the next available byte to the SPI send buffer.
"The master will send 10, 3F,00 and slave will take these
And the slave will send 00,00,33 and the master will take these"
If it is assumed that the slave is expected to respond with 0x33 after the master has sent 0x10, 0x3F as a "command" - a typical situation - and that the 0x00 are "dummy" bytes, here would be the sequence of events -
- Slave puts 0x00 in its send buffer (null data), ready for next transaction by master.
- Master sends 0x10 and receives 0x00.
- Slave receives 0x10 and puts 0x00 in send buffer (or does nothing).
- Master sends 0x3F and receives 0x00.
- Slave receives 0x3F, and determines that it needs to return 0x33, so puts this value in send buffer.
- Master sends 0x00 (dummy), and receives 0x33.
- Slave receives 0x00, and puts 0x00 in send buffer.
"for my codes; i want to send these information that 'M','A','S','T','E','R' from master to slave. And these 'S','L','A','V','E','00', are from slave to master. could you say me any way?"
- Slave puts 'S' in its send buffer ready for next transaction by master.
- Master sends 'M' and receives 'S'.
- Slave receives 'M' and puts 'L' in send buffer.
- Master sends 'A' and receives 'L'.
... and so on.
"MOSI is connected to MOSI
MISO is connected to MISO
SCK is connected to SCK
SS is connected to Vcc=5V on master side
and SS is connected to gnd=0V on slave side
are these connections true?"
You are basically correct, provided there is a single slave device, and you operate with SPI parameter CPHA = 1. If CPHA = 0, the master will need to raise slave /SS input high after each transfer (this may be a GPIO line at the master, to control the slave /SS). With more than one slave, the master device would need to provide a separate line to control each slave.
The code example given below is for the master and does not use interrupts. It shows the method of monitoring the SPI flags. The corresponding code for the slave would be more complex because of the ISR process and the provision of a FIFO buffer, and is not currently shown.
Making a few basic assumptions, suitable SPI initialisation values for the master might be -
SPICR1 = 0x54;
SPICR2 = 0x00;
You will also need to initialise SPIBR to a suitable value. The following is a function to provide a master transaction -
byte SPI_proc (byte send_byte)
while (!SPISR_SPTEF); /* Wait for Tx buffer empty */
SPIDR = send_byte;
while (!SPISR_SPIF); /* Wait for Rx buffer full */
For the three master operations in the example shown above, consider the following sequence -
SPI_proc(0x10); /* Send first command byte & ignore return */
SPI_proc(0x3F); /* Send second command byte & ignore return */
slave_val = SPI_proc(0); /* Send dummy byte & receive slave value */
Message Edited by bigmac on 03-24-200608:52 PM