S12XET256 doesn't reset always with COP enabled

[emanuelecastagn]

Hi all, I've a board in which I use S12XET256 controller, initialized only once with COPCTL=0x41 (or 0x01). I have a very noisy environment with inductive loads (motor power contactors) that switch on and off at any motor run. I mostly see a reset from COP properly working especially when inductive load is switched off, even if I have RC filter and varistor on the contactor's coil, but sometimes board remains locked, with oscillator ON and reset at 5V. Has anyone some suggestion for this problem? Many thanks, Emanuele.

[RadekS]

Hi Emanuele,

We could assume several potential scenarios:

1. Since you wrote about very noisy environment and you wrote 0x41 into COPCTL, it is possible, that MCU was reset into special mode (BKGD pin is temporary low). Could you please try 0x01 as COPCTL value or little bit play with external pull-up and capacitor at BKGD pin?
2. It is possible that MCU lost clock. Please check whether you enabled clock monitor (PLLCTL_CME) and value of Self Clock Mode Enable Bit (PLLCTL_SCME).
3. It is possible that you try initialize PLL before you enable COP. It is recommended to read back the PLLSEL bit to make sure PLLCLK has really been selected as SYSCLK, as LOCK status bit could theoretically change at the very moment writing the PLLSEL bit. For example:

while(!CLKSEL_PLLSEL)  // PLLSEL=1 check

  { while(!CRGFLG_LOCK); // Wait till the PLL VCO is within tolerance

CLKSEL_PLLSEL = 1;  // Select clock source from PLLCLK

  }

    4. Some customers don’t use PLL in noisy environment. It is correct, but we have to do not forget on PLL configuration settings. SYNR, REFDV and POSTDIV registers should contain valid values because PLLCLK is used for validate oscillator clock.

I hope it helps you.

Have a great day,
RadekS

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[emanuelecastagn · Accepted solution]

Hi RadekS, many thanks for your prompt reply and proper suggestions.
I've done a lot of tests, if I remember properly also with 0x01 in COPCTL (I will try again). I have COP init done before PLL init.
Before to open this ticket, i've tried COP init done after in a test and before in another test, without any good result.
Now I've added a 10uF electrolitic capacitor in parallel to reset signal and the problem does not appear anymore.
Probably a spurious and impure reset cause this kind of problem, this is the reason why, in the previous ticket, I asked if it was possible to disable reset input after inizialization, but now I know I can't.
I've attached my reset circuitry, in which now there is a 10uF electrolytic capacitor in parallel to C10.
Many thanks for any kind of suggestion, best regards, Emanuele.

[RadekS]

Hi Emanuele,

I am glad that it works now.

In fact, noise immunity will probably mainly depend on length of reset signal on your pcb.

Disadvantage of such high capacitor at RESET pins is slow changing. In your case (1KOhm, 1uF) it preset 1ms delay. In such case, we cannot correctly distinguish between COP, CM or external RESET pin reset source.

However as I see, you also using power supply supervisor circuit. In this case it doesn’t matter, because FM809 guarantee that the reset pulse will be valid for a minimum of 140ms (256ms typical).

Note: for MCU itself, you don’t need such supervisor circuit. S12XE already contains low voltage interrupt (app. 4.3V) and low voltage reset (app. 3V) features. But external supervisor circuit could be useful in some cases and for other external devices… It depends on you specific use case.

I hope it helps you.

Have a great day,
RadekS

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