Default state of CPU HCS12 XEP100 and Processor Expert

[grzegorzK]

Dear

I have one problem:

HW: HCS12X (XEP100), CodeWarrior + PE

I have written firmware bootloader in order to download and later on upgrade application.

case 1:

When I start application without bootloader (just flash application) than everythink works well.

case 2:

When I first flash bootloader, than using bootloader will download application, than strange think happen:

periodic IRQ from one timer is not working with desired period but much, much less (50 times?). It is quite strange because all application works well beside this IRQ. Application call ISR of this timer what is proof IRQ vector is OK, it is different IRQ offset from bootloader (is set in cpu.c), what I have tested but is called with other period.

Study:

- Both: bootloader and application use Processor Expert.

- bootloader start first and after all itself initialization call _EntryPoint() of application, so I expect _EntryPoint() will do all initialization work and all timers and PLL settings should works as without bootloader (see case 1).

- the only difference between application from case 1 and case 2 is address of _ResetVectorTable[] (from vectors.c generated by PE) due vectors from application and bootloader should not overlap.

So from my testing I suspect that something is wrong with CPU and/or peripheral (PLL? clock division?) state after initialization in case 2!

1. So my question is: How to secure default CPU state when call application under bootloader (both using Processor Expert for initialization).

In other words I suspect that

a) hardware or software reset and start from _EntryPoint() of bootloader than call _EntryPoint() of application

  is not equivalent of:

b) hardware or software reset and than start from _EntryPoint() of application.

2. Any other suspect in this problem?

Best Regards

/Greg

[RadekS]

From your descriptions it really looks like problem with PLL.

You didn’t mention which timer you using.

1. You have two _EntryPoint() functions. I suppose that both functions will execute more less the same code. And this could presents problem in case of some registers (some bits), which are write once. For example PLLCTL_SCME…

1. I suppose that both _EntryPoint() functions contains PLL initialization code. So you initialize PLL, disable PLL and Initialize PLL again in very short time.

Automatically generated code from PE contains simple while loop for waiting to CRGFLG_LOCK bit:

while(CRGFLG_LOCK == 0U) {           /* Wait until the PLL is within the desired tolerance of the target frequency */

  }

  /* CLKSEL: PLLSEL=1 */

  setReg8Bits(CLKSEL, 0x80U);          /* Select clock source from PLL */

There is theoretically chance for unlocking PLL between while loop end and set PLLSEL bit. Therefore I would like recommend use this part of code (or similar):

while(!CLKSEL_PLLSEL) // PLLSEL=1 check

  { while(!CRGFLG_LOCK); // Wait till the PLL VCO is within tolerance

    CLKSEL_PLLSEL = 1;   // Select clock source from PLLCLK

  }

[grzegorzK]

Hi

Thank you Radek, you are helpful like always.

I have checked PLL, all works fine! other peripherals what use PLL source clocks works great. Check also all value direct in registers.

I have found root problem.

As you say, I did not provide type of timer, it is ECTTC0.

1. This timer is used in bootloader and application!

2. both use it as source of ISR, but with different period

problem is:

3. Processor Expert in application do not set (in fact re-init) it properly with proper period!

Suppose I may find resolution reading some documentation, however

May someone know quick, simply and easy fix to set ECTTC0 in application (ECTTCO was already set once by Processor Expert in bootloader)?

[RadekS]

Could you please put here your ECT init functions (from bootloader and from application codes)?

I hope that after that we can more easily found some quick, simply and easy fix.  

[grzegorzK]

Hi

In magenta bootloader (there are 2 timers connected with this peripherial).

In blue, application.

What looks significant: different clock, 50000000Hz i application, and 195312Hz in bootloader.

** Abstract  :

**         This component "TimerInt" implements a periodic interrupt.

**         When the component and its events are enabled, the "OnInterrupt"

**         event is called periodically with the period that you specify.

** TimerInt supports also changing the period in runtime.

**         The source of periodic interrupt can be timer compare or reload

** register or timer-overflow interrupt (of free running counter).

** Settings  :

**         Timer name                  : ECT_Counter (16-bit)

** Compare name                : ECTTC0

** Counter shared              : Yes

**

**         High speed mode

** Prescaler               : divide-by-1

** Clock                   : 195312 Hz

** Initial period/frequency

** Xtal ticks              : 3994

**             microseconds            : 998

** milliseconds            : 1

** seconds (real)          : 0.0009984

** Hz                      : 1002

** kHz                     : 1

**

** Runtime setting             : none

**

** Initialization:

** Timer                  : Enabled

** Events                 : Enabled

**

**         Timer registers

** Counter                : ECT_TCNT  [$0044]

** Mode                   : ECT_TIOS  [$0040]

** Run                    : ECT_TSCR1 [$0046]

** Prescaler              : ECT_TSCR2 [$004D]

**

** Compare registers

** Compare                : ECT_TC0   [$0050]

**

** Flip-flop registers

** Mode                   : ECT_TCTL2 [$0049]

setReg8(INT_CFADDR, 0xE0U);

setReg8(INT_CFDATA7, 0x03U);         /*  0x77 0xFFEE   3   no ivVectch0       used by PE */

(...)

  /* ECT_TSCR1: TEN=0,TSWAI=0,TSFRZ=0,TFFCA=0,PRNT=1,??=0,??=0,??=0 */

setReg8(ECT_TSCR1, 0x08U);

  /* ECT_MCCTL: MODMC=1 */

setReg8Bits(ECT_MCCTL, 0x40U);

  /* ECT_OCPD: OCPD1=1,OCPD0=1 */

setReg8Bits(ECT_OCPD, 0x03U);

  /* ECT_PACTL: CLK1=0,CLK0=0 */

clrReg8Bits(ECT_PACTL, 0x0CU);

  /* ECT_OC7M: OC7M1=0,OC7M0=0 */

clrReg8Bits(ECT_OC7M, 0x03U);

  /* ECT_TIOS: IOS1=1,IOS0=1 */

setReg8Bits(ECT_TIOS, 0x03U);

  /* ECT_TCTL2: OM1=0,OL1=0,OM0=0,OL0=0 */

clrReg8Bits(ECT_TCTL2, 0x0FU);

  /* ECT_TTOV: TOV1=0,TOV0=0 */

clrReg8Bits(ECT_TTOV, 0x03U);

  /* ECT_TSCR2: TCRE=0 */

clrReg8Bits(ECT_TSCR2, 0x08U);

  /* ECT_TFLG1: C7F=1,C6F=1,C5F=1,C4F=1,C3F=1,C2F=1,C1F=1,C0F=1 */

setReg8(ECT_TFLG1, 0xFFU);

  /* ECT_TIE: C1I=0,C0I=1 */

clrSetReg8Bits(ECT_TIE, 0x02U, 0x01U);

  /* ECT_PTPSR: PTPS7=1,PTPS6=1,PTPS5=1,PTPS4=1,PTPS3=1,PTPS2=1,PTPS1=1,PTPS0=1 */

setReg8(ECT_PTPSR, 0xFFU);

(...)

  /* ### TimerInt "timer_1ms_period" init code ... */

  /* ECT_TC0: BIT15=0,BIT14=0,BIT13=0,BIT12=0,BIT11=0,BIT10=0,BIT9=0,BIT8=0,BIT7=1,BIT6=1,BIT5=0,BIT4=0,BIT3=0,BIT2=0,BIT1=1,BIT0=1 */

setReg16(ECT_TC0, 0xC3U); /* Store given value to the compare register */

(...)

  /* ### Free running 16-bit counter "benchmark_timer" init code ... */

  /* ECT_TC1: BIT15=1,BIT14=1,BIT13=1,BIT12=1,BIT11=1,BIT10=0,BIT9=1,BIT8=1,BIT7=1,BIT6=1,BIT5=0,BIT4=0,BIT3=1,BIT2=0,BIT1=0,BIT0=0 */

setReg16(ECT_TC1, 0xFBC8U); /* Store given value to the compare register */

  /* Common peripheral initialization - ENABLE */

  /* ECT_TSCR1: TEN=1,TSWAI=0,TSFRZ=0,TFFCA=0,PRNT=0,??=0,??=0,??=0 */

setReg8(ECT_TSCR1, 0x80U);

Header from module in applicatation and belowe propably code from cpu.c

------------------------------------------------------------------------------------------------

** Abstract  :

**         This component "TimerInt" implements a periodic interrupt.

**         When the component and its events are enabled, the "OnInterrupt"

**         event is called periodically with the period that you specify.

** TimerInt supports also changing the period in runtime.

**         The source of periodic interrupt can be timer compare or reload

** register or timer-overflow interrupt (of free running counter).

**     Settings :

**         Timer name                  : ECT_Counter (16-bit)

** Compare name                : ECTTC0

** Counter shared              : No

**

**         High speed mode

** Prescaler               : divide-by-1

** Clock                   : 50000000 Hz

** Initial period/frequency

** Xtal ticks              : 4000

** microseconds            : 1000

** milliseconds            : 1

** seconds (real)          : 0.001

** Hz                      : 1000

** kHz                     : 1

**

** Runtime setting             : none

**

** Initialization:

** Timer                  : Disabled

** Events                 : Enabled

**

**         Timer registers

** Counter                : ECT_TCNT  [$0044]

** Mode                   : ECT_TIOS  [$0040]

** Run                    : ECT_TSCR1 [$0046]

** Prescaler              : ECT_TSCR2 [$004D]

**

** Compare registers

** Compare                : ECT_TC0   [$0050]

**

** Flip-flop registers

** Mode                   : ECT_TCTL2 [$0049]

** Contents  :

setReg8(INT_CFADDR, 0xE0U);          

setReg8(INT_CFDATA7, 0x04U);         /* 0x77  0x7FEE   4   no   ivVectch0       used by PE */

(...)

  /* ECT_TSCR1: TEN=0,TSWAI=0,TSFRZ=0,TFFCA=0,PRNT=0,??=0,??=0,??=0 */

setReg8(ECT_TSCR1, 0x00U);

  /* ECT_MCCTL: MODMC=1 */

setReg8Bits(ECT_MCCTL, 0x40U);

  /* ECT_OCPD: OCPD7=1,OCPD6=1,OCPD5=1,OCPD4=1,OCPD3=1,OCPD2=1,OCPD1=1,OCPD0=1 */

setReg8(ECT_OCPD, 0xFFU);

  /* ECT_PACTL: CLK1=0,CLK0=0 */

clrReg8Bits(ECT_PACTL, 0x0CU);

  /* ECT_OC7M: OC7M0=0 */

clrReg8Bits(ECT_OC7M, 0x01U);

  /* ECT_TIOS: IOS7=1,IOS0=1 */

setReg8Bits(ECT_TIOS, 0x81U);        

  /* ECT_TCTL2: OM0=0,OL0=0 */

clrReg8Bits(ECT_TCTL2, 0x03U);

  /* ECT_TTOV: TOV7=0,TOV0=0 */

clrReg8Bits(ECT_TTOV, 0x81U);

  /* ECT_TCTL1: OM7=0,OL7=0 */

clrReg8Bits(ECT_TCTL1, 0xC0U);

  /* ECT_TSCR2: TOI=0,TCRE=1,PR2=0,PR1=0,PR0=0 */

clrSetReg8Bits(ECT_TSCR2, 0x87U, 0x08U);

  /* ECT_TIE: C0I=0 */

clrReg8Bits(ECT_TIE, 0x01U);

(...)

  /* ### TimerInt "TI1_SchedulerTimer" init code ... */

  /* ECT_TC0: BIT15=1,BIT14=1,BIT13=0,BIT12=0,BIT11=0,BIT10=0,BIT9=1,BIT8=1,BIT7=0,BIT6=1,BIT5=0,BIT4=1,BIT3=0,BIT2=0,BIT1=0,BIT0=0 */

setReg16(ECT_TC0, 0xC350U); /* Store given value to the compare register */

  /* ECT_TC7: BIT15=1,BIT14=1,BIT13=0,BIT12=0,BIT11=0,BIT10=0,BIT9=1,BIT8=1,BIT7=0,BIT6=1,BIT5=0,BIT4=1,BIT3=0,BIT2=0,BIT1=0,BIT0=0 */

setReg16(ECT_TC7, 0xC350U); /* Store given value to the modulo register */

[RadekS · Accepted solution]

I shortly checked your codes and I am sure that issue is in TSCR1_PRNT bit.

You used Precision Timer in bootloader and not in application. Unfortunately TSCR1_PRNT bit can be written just once. Therefore you got different frequency.

[grzegorzK]

works.

thank you!

[grzegorzK]

I will test, and let you know.

Thank You.

[grzegorzK]

Is it better to attach CPU.c files from both projets?

Time registers from description are the same (e.g. ECT_TSCR2 ) but different is clock source (I suppose).

/Greg