Built in Error Detection and Correction and/or Self Test available?

[Falk]

Is there any information available if Error Detection and Correction Codes (EDCC/ECC) or Built in Self Test (BiST) are present in current freescale devices or if there are plans to include them?

I have the following measures in mind:

• ECC for protection of code memory (can be done in software, but it would be nice to have it in hardware)
• ECC for RAM and registers
• Built in self test to monitor the CPU and built in peripherals (cyclic or at start up?)
• ...

These measures might be of great interest in safety critical applications as future drive-by-wire systems.

Thanks for your help

Falk

[Alban]

Hello Falk,

When ECC is available on the MCU, it is advertised. By default S12 don't feature ECC for Flash, but a few models are.

BiST is not available to customers. Other principles are implemented for safety critical applications: to cite a couple, memory violation protection schemes and use of XGATE co-processor (on S12X) for challenge-response or as an execution supervisor/controller.

(also Windowed COP...)

Alban.

[Falk]

Hello Alban,

Thanks for your fast reply! Some more questions:

1. Is there an overview which devices offer ECC for flash?
2. Is there an application note available for using the XGATE co-processor for monitoring purposes?
3. Any document one could read to get more information about the principles for safety critical applications you mentioned?
4. What exactly is windowed COP?

Regards

Falk

[Alban]

Hi Falk,

1 - I would recommend the brand new S12XE family with also ECC on E²PROM (actually EEEPROM).

http://www.freescale.com/files/microcontrollers/doc/support_info/MC9S12_X_FAMILIES.pdf

http://www.freescale.com/files/automotive/doc/roadmap/S12-S12XAUTOROADMAP.pdf

The MC9S12KG also features Flash ECC, as well as MC9S12KT256. I don't know if they are recommended for new designs.

2 - I don't think there is any specific for that. As ideas, you can use the XGATE to calculate checksums on the RAM and check with a checksum the CPU12X have calculated. Only allow certain actions if both the XGATE and CPU12X agree on the same calculation.

As they are differentes core (XGATE is RISC, CPU12X is CISC), the same C code will be compiled a different way, but you call also run two different algorithms and check the result of the data...

You can use the XGATE independantly.

On the S12XE, you even have a Supervisor State, where control is different. You can set special memory access to the core(s) you want on the memory are you want. It is the perfect way to prevent a task from corrupting memory from another task.... There are so many solutions that a post is not enough.

3 - There are quite a lot in fact. Freescale Technology Forum materials does show few very interestings aspects and how to use these features.

I can see:

http://www.freescale.com/files/ftf_2006/doc/presentations/Paris/FA106.pdf

Look for FTF presentations on freescale.com.

4 - A Windowed Computer Operating Properly is a watchdog expecting a refresh between certain times. Meaning that you not only say it needs to be refreshed often enough (to prevent time-out), but it means it needs to be refreshed at a certain time.

This allowed time frame is called the window.

The application is more robust as any wrong behaviour is detected earlier and you can detect more wrong behaviour with a stricter COP.

Most of what I said here is taken from Application Notes and FTF Presentations.

Cheers,

Alban.

[Falk]

Thanks a lot!

The FTF pages seem to contain a lot of useful information. i will have a closer look at them.

Cheers

Falk

[Falk]

http://www.freescale.com/files/ftf_2006/doc/presentations/Milan/YA101.pdf is especially interesting...

Falk