Can two entries of the T1042 LAW have the same target ID?
I am getting an exception on a custom board when writing to my DDR. Here are my LAW settings:
I can write to RAM with JTAG in CodeWarrior. Yet U-BOOT SPL running out of SRAM does hits an exception:
SPI boot (SPL Version: U-Boot 2016.09)...
Initializing....using SPD
Testing DDR bytelanes...
Writing memory...
lane0 0
Bad trap at PC: fffdb114, SR: 21200, vector=300
**bleep**: FFFDB114 XER: 00000000 LR: FFFDB114 REGS: fffd7eb0 TRAP: 0300 DAR: 00000000
MSR: 00021200 EE: 0 PR: 0 FP: 0 ME: 1 IR/DR: 00
GPR00: FFFDB114 FFFD7FA0 FFFC8000 00000008 0000000A FFFD7D08 FFFFFFFC 00000020
GPR08: 00000001 00000020 FFFD7E4F FFFD7FA0 FFFDD254 0000A3E0 00000000 FFFFFFFA
GPR16: 00000000 77EE40C0 DF900700 00000000 00001000 FFFD7EA0 00000000 FFFD9FC0
GPR24: FFFE256F FFFFFFFF FFFE2579 00000000 00000000 80000000 FFFE175C 00000000
Call backtrace:
Exception in kernel pc fffdb114 signal 0
Two entries of the T1042 LAWs could have the same target ID.
Please check DDR controller configuration.