T1022-DDR4 Clock and strobe length Issue.

取消
显示结果 
显示  仅  | 搜索替代 
您的意思是: 

T1022-DDR4 Clock and strobe length Issue.

1,029 次查看
rampal
Contributor I
Hi,
we are using DDR4 with T1022 processor. In App-note  AN5097_rev.1, it is given that "The clock signal trace length from the memory controller to any given DDR4 chip should be longer than its corresponding strobe trace length." 
In further sections it is also given that " In the case that the clock trace length is shorter, the following limits must be observed:  The clock trace length can be a maximum of 2.0 inches shorter than the strobe trace length for a given byte lane."
presently my clock length is shorter than longest strobe by 1 inch. is it okay, or should I increase my clock's length?
I also heard of write leveling for such issues. How much skew can we compensate  by that?
I also want to now that, in this write leveling, we adjust (DELAY) clock or we adjust (Advance)  MDQS?
Is it a byte wise adjustment (means we adjust MDQS and clock for each 8 byte lanes differently) or a single adjustment for all 8 data byte lane?
标记 (3)
0 项奖励
4 回复数

946 次查看
rampal
Contributor I

Thank you.

We are using a single DDR4 VLP mini-UDIMM module (D31.23185S.001).
I was just concern that my clock lengths are smaller than strobe by 1 inch maximum. Will it work? Can we compensate this using write leveling?
0 项奖励

946 次查看
Bulat
NXP Employee
NXP Employee

As I already wrote, you meet AN5097 limits, so the DDR controller will work.

Regards,

Bulat

0 项奖励

946 次查看
rampal
Contributor I

Ok, Thank you so much.

0 项奖励

946 次查看
Bulat
NXP Employee
NXP Employee

Do you use fly-by topology? In this case it is difficult to get MCK traces shorter than MQDS ones. Anyway, you meet AN5097 limits.
Write leveling adjusts MDQS delays individually for each byte lane.

Regards,

Bulat

0 项奖励