SERDES clock in t2081

[monalihaware]

I have a custom board with t2081 processor. And in the process of bringing it up,  using Hard coded RCW. And over writing the RCW values using JTAG config file in code warrior.

SD1_REF_CLK1_P and SD1_REF_CLK1_N are attached to clock generators IC.

SD1_REF_CLK2_P and SD1_REF_CLK2_N are not connected to any clock generators. In fact the left "not conncetd" as shown in the snap attached.

Is it mandatory to connect SD1_REF_CLK2_P, SD1_REF_CLK2_N  to be connected clk source for board bring up?

                                                                                    OR

Can i just over write the PLL1,PLL2 to be 'disabled' in the JTAG config file as there is no option now to change the hardware connections.

Can any one help in this? I am stuck here.

[monalihaware]

Hi Serguei Podiatchev,

Thanks a lot. I was worried cuz i cant change the board harware now. Thanks again

[r8070z]

Have a great day,

It is not mandatory to connect SD1_REF_CLK2_P, SD1_REF_CLK2_N to clk source for board bring up. The manual says “After completing reset, software should check the SerDesx_PLLnRSTCTL[RST_DONE] field to make sure that each active SerDes PLL on the device has locked.” You should set PLL2 power down in  RCW[SRDS_PLL_PD_S2].

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