Reset vector for T1024


Reset vector for T1024

Contributor II


     From the reference manual of T1024 processor, the reset vector is 0xFFFFFFFC.

we are using NOR flash as boot device. NOR flash is connected on CS0 of IFC bus.

and NOR flash is 128 MB size, address range is 0x40000000 to 0x47FFFFFF

so can you please tell me which location in NOR flash is mapped to this Reset vector of T1024 processor?

is there any power architecture feature says 768K from the end of NOR flash will be mapped to this reset vector location?

or the last address of NOR flash (0x47FFFFFC) will be mapped to reset vector address (0xFFFFFFFC)

0 件の賞賛
1 返信

NXP TechSupport
NXP TechSupport

Have a great day,

After reset, until a first write transaction occurs to update AMASK0 register, all the transactions coming from the system side will always be mapped to CS0.

I suppose you connect your NOR flash for normal mode /* ADM_SHFT_MODE = 0 and cfg_rcw_src[6:7] =10 (00 28b addressability) */. So only 27 least significant bits of the transactions address are applied. Hence reset vector of T1024 processor is taken from location 0xFFFFFFFC & 0x7FFFFFF = 0x7FFFFFC in your NOR flash.

So when you map your NOR to 0x40000000 to 0x47FFFFFF this location is at 0x47FFFFFC.

Note: If this post answers your question, please click the Correct Answer button. Thank you!

0 件の賞賛