On the qd tdm port, how to configure the ucc fast mode, do not issue the crc check

[1271792207]

Hello!
   I am now debugging qe's tdm port, this port is controlled by ucc, ucc works in fast mode. When sending data, ucc will send a 2 byte 16bitcrc check after sending a bd buffer. After I remove the send crc check, the crc check will not be sent, but the two time slots will be vacant and set to high level. How to call this time slot is removed.

for (i = 0; i < TX_BD_RING_LEN; i++) {
if (i < (TX_BD_RING_LEN - 1))
bd_status = 0 ; 
else
bd_status = T_W_S;

iowrite16be(bd_status, &priv->tx_bd_base[i].status);
iowrite32be(priv->dma_tx_addr + i * MAX_RX_BUF_LENGTH, &priv->tx_bd_base[i].buf);
}

If bd_status = T_TC_S;
A 16-bit crc is sent after each bd is sent.
If bd_status = 0, crc will not be issued, but 0xff will be sent.
How to get rid of not sending things.

  Anyone who can help me solve this problem, thank you very much.

[alexander_yakov]

The number of bytes transferred per TDM frame is configured in TDM SI ram settings, but not in UCC. When you configure UCC to send CRC16, this appends two extra bytes to frame, and these two extra bytes are sent through two TDM entries in TDM frame. When you reconfigure UCC to not send CRC data, this causes UCC to send only payload, without these two extra bytes of CRC, but TDM SI ram configuration still has these extra entries, so these extra two TDM slots are filled with  0xFF data.

Have a great day,
Alexander,
TIC

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[1271792207]

You are right, thank you very much.

[1271792207]

Sorry, I re-tested that the number of free slots is related to whether the length of the bdbank can be divisible by the number of slots you have configured. If it can be divisible, but there will still be a spare time slot after the completion of a bdbank is not filled with data. how to solve this problem.