How to Select PLL for SerDes Interface

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How to Select PLL for SerDes Interface

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matthej
Contributor II

I see that each SerDes (1 and 2) have two PLLs each (1 and 2).

 

I don't see where in the manual you are able to select which PLL you want to use for which SerDes interface.

I see this register for example, but it doesn't seem to be tied to a particular SerDes

 

How do I assign PLL1 for SerDes1 and PLL2 for SerDes2 for example?

 

Thanks!

 

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Bulat
NXP TechSupport
NXP TechSupport

Yes, PLL2 is used for all lanes in your example.

The muxer allows to use a single reference clock (SD1_REF_CLK1) for both PLL's. Yes, if you apply clocks to both inputs (SD1_REF_CLK1 and SD1_REF_CLK2), the muxer allows to select which clock is used as a reference for PLL2.

Regards,

Bulat

 

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Bulat
NXP TechSupport
NXP TechSupport

Your forgot to point out NXP device in the question.

For QorIQ devices the user can not explicitly select/assign PLLs for SERDES interfaces. All possible PLL to SERDES_lane assignments are made in hardware and depend on the SERDES configuration the user wants to use. SERDES configuration is defined by RCW configuration and happens when the processor comes out of reset.

PLL to SERDES lanes mapping can be found in the reference manuals. See chapter "SerDes Module", first table of the chapter provides all possible configuration options of the SerDes. The first column shows RCW configuration options, the last column shows PLL's mapping to lanes. For example, mapping '2111' means PLL2 is assigned to lane #0, PLL1 is assigned lanes #1, #2, #3.

Regards,

Bulat

 

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matthej
Contributor II

Ok I am using the LS1046A device.

 

So I want to run 1Gbps SGMII on SD1_RX0/TX0, SD1_RX1/TX1, and SD1_RX2/TX2.

 

I can then choose RCW[128-143] = 3333, which gives me PLL2 for all lanes? And since I have a ref clock on both SD1_REF_CLK1 and SD1_REF_CLK2 inputs on my board I can select either one since there is a mux (see photo below)

matthej_0-1635421204584.png

matthej_1-1635421304703.png

 

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Bulat
NXP TechSupport
NXP TechSupport

Yes, PLL2 is used for all lanes in your example.

The muxer allows to use a single reference clock (SD1_REF_CLK1) for both PLL's. Yes, if you apply clocks to both inputs (SD1_REF_CLK1 and SD1_REF_CLK2), the muxer allows to select which clock is used as a reference for PLL2.

Regards,

Bulat

 

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