This is with regarding to processor P2040.
Is it possible to make any GPIO accessible at PBL stage only, that is, we can toggle the GPIO when we are at PBL booting stage and after PBL stage no one can access that GPIO.
Also, NOR (GPCM) doesn't has any dedicated Write protect signal, which GPIO can be used to achieve this (write protect) functionality.
> Is it possible to make any GPIO accessible at PBL stage only
This is not possible at the processor level. Possible solution is to implement an external gate for a GPIO signal.
> Also, NOR (GPCM) doesn't has any dedicated Write protect signal
It is up to the designer which GPIO signal to use for implementing required functionality.
Thanks for your clarification on the GPIO accessibility. I would like to add one more point in the above discussion that we have LGTA signal in GPCM which terminates the external access to the NOR. Can we use this signal as write protect?