Hello
I am using DSC (56F84567) as master SPI. the slave chip read data bit on clock rising edge. However, setting the SPI clock to "rising edge" dont give any setup time to data to be stable before sending the clock, so the slave can't read the data.
When setting the clock polarity to falling edge, the clock is shifted and the slave can read the data on rising edge.
Is there a way in SPI component to set the data stabilization time by shifting the clock?
Hi, Benny,
First of all, can you tell us the signal name for the screenshot of the scope?
BTW, I see that the SPI of MC56F84567 is master, based on the SPI protocol, when the SPI is idle, the /SS pin should be high, there should not be clock signal within the high logic of /SS.
Can you tell us whether the /SS signal is generated by the SPI module itself or GPIO pin controlled by firmware?
This is the SPI timing:
From above spi timing, you can see that the rising edge of SCLK triggers the data pin MOSI to be valid, falling edge of SCLK will latch the data pin on the slave SPI receiver. So the setting up time is half clock cycle time of SCLK, the holding time is the half of the SCLK cycle time.
BR
XiangJun Rong
