ADC issue with CW 10.6

[djmoore]

Hi All,

I had an SCI issue with CW 10.4 and installed 10.6 which fixed it, looks like the Enter Critical wasn't disabling interrupts

as the Buffer was good, but the output pointer was getting corrupted.

Now I have a new problem, the ADC code which was working in 10.4 has an issue. One channel looks to be reading the

wrong port (now confirmed) (ADC0_SE4B pin 21, KL25 80 pin package)

I've tracked down the issue to the following bit in the ADC Init code, produced by Code warrior PE.

LDD_TDeviceData* AdcLdd1_Init(LDD_TUserData *UserDataPtr)

...snip..

/* ADC0_CFG2: MUXSEL=0,ADACKEN=0,ADHSC=0,ADLSTS=0 */

  ADC0_CFG2 &= (uint32_t)~(uint32_t)(

//                ADC_CFG2_MUXSEL_MASK |

                ADC_CFG2_ADACKEN_MASK |

                ADC_CFG2_ADHSC_MASK |

                ADC_CFG2_ADLSTS(0x03)

               );

With CW 10.6, the ADC Init code clears the MUXSEL, to choose the 'a' ADC input pins, the only ADC input I'm using

in the 'a'/'b' banks is ADC0_SE4b, pin 21 on the 80pin KL25 package. So PE is selecting the wrong bank.

Regards,

Darren

KL25P80M48SF0RM.pdf

Chapter 28 Analog-to-Digital Converter (ADC)

page 467

4 MUXSEL

ADC Mux Select

Changes the ADC mux setting to select between alternate sets of ADC channels.

0 ADxxa channels are selected.

1 ADxxb channels are selected.

[djmoore]

BTW, here is some more of the Init code, which you can see the MUXSEL bit is set high in the first line as it  should

be, only to be cleared a few lines later... :smileyconfused:

  /* ADC0_CFG2: MUXSEL=1 */

  ADC0_CFG2 |= ADC_CFG2_MUXSEL_MASK;

  /* ADC0_CFG1: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,ADLPC=0,ADIV=3,ADLSMP=1,MODE=1,ADICLK=0 */

  ADC0_CFG1 = ADC_CFG1_ADIV(0x03) |

              ADC_CFG1_ADLSMP_MASK |

              ADC_CFG1_MODE(0x01) |

              ADC_CFG1_ADICLK(0x00);

  /* ADC0_CFG2: MUXSEL=0,ADACKEN=0,ADHSC=0,ADLSTS=0 */

  ADC0_CFG2 &= (uint32_t)~(uint32_t)(

                ADC_CFG2_MUXSEL_MASK |

                ADC_CFG2_ADACKEN_MASK |

                ADC_CFG2_ADHSC_MASK |

                ADC_CFG2_ADLSTS(0x03)

               );

[Petr_H · Accepted solution]

Hi,

you are right,  we have reproduced the problem and classified it as a bug.

The problem appears when you are using pins with 'b' (e.g. ADC0_SE4B). In such case the ADC_CFG2_MUXSEL field is incorrectly cleared in CFG2 register.

We are sorry for an inconvenience. The fix for the problem is being prepared and will be available in a short time.

As a temporary workaround, please place the following line after the AdcLdd1_Init call (or if you using "auto initialization" feature, after the   /*** End of Processor Expert internal initialization. ):

In case you are using ADC0:

ADC0_CFG2 |= ADC_CFG2_MUXSEL_MASK;

In case you are using ADC1:

ADC1_CFG2 |= ADC_CFG2_MUXSEL_MASK;

Best regards

Petr Hradsky

Processor Expert Support Team

[djmoore]

Hi Petr,

Thanks for confirming the issue.

Your solution is the same is what I used to patch around it.

Regards,

Darren

[Petr_H]

Please find attached a hot-fix package that fixes the problem for CodeWarrior 10.6.

best regards

Petr Hradsky

Processor Expert Support Team