RCW(Reset Configuration Words) Sources for MPC8349E

[youngho_cho]

Hello, NXP engineers and all members of the community group.

I am working on a new board development using the MPC8394E processor.
Various other configurations were designed by getting a reference through the EVM board, etc.

I have additional questions.

According to the document AN2931,
If RCW is stored in a flash on the local bus like our system, there is an issue that the CPU core does not work because during the PORESET process, the device cannot read the RCW value before the valid RCW value is written to the flash.

In this case, there are 3 options.

Among them, first of all, if the RCW value is read with the hard-coded option, is this value saved in the boot loader?

Also, in the case of the hard-coded option, the device is shown to operate in PCI agent mode.

As in the previous inquiry, all peripherals are controlled through specific controllers or local bus controller and our system will not use the PCI bus at all.

Wouldn't it be a problem to the system operation even if booted in PCI agent mode?

Secondly, as designed as BCSR in the MPC8349EAMDSPB, if RCW value is provided as logic through CPLD or FPGA during POR, is this value input through the local bus?
Before the device core wakes up, is it possible to access the local bus and read the values written to the FPGA?

Please answer about my question.

[r8070z]

There are several hard-coded default options, selected by the reset configuration input signals, CFG_RESET_SOURCE[0:2]. Hard-coded reset configuration words are driven internally and and do not appear on any MPC834x interface. All hard-coded configuration words set

PCIHOST=0 PCI agent mode

PCI1ARB=0 External arbiter is used.

COREDIS=1 e300c1 core is disabled (boot holdoff)

BOOTSEQ=00 Boot sequencer is disabled

More details you can find in the section 4.4.3.3 Default Reset Configuration Words of the MPC8349 reference manual

These setting can be unsolvable problem for your system if there is no external PCI host which can enable the core.

Typically RCW value from CPLD or FPGA during POR loaded using the local bus. Hoever if your FPGA has PCI host port then it can configure the MPC8349 PCI agent.

>Before the device core wakes up, is it possible to access the local bus and read the values written to the FPGA?

Yes it is possible.