In my design, the PMIC will be powered by a 5V switching regulator. The 5V is generated from a 24V supply. In normal operation, the PMIC takes care of correct power down sequencing.
My question is related to power supply failures and short circuit in 24V. If violation of the power down sequence can cause damage to the processor, I would need to keep my 5V supply alive for at least 64ms even without a 24V supply, which can fail instantly in case of short circuit. This is not impossible, but would require some additional circuitry and capacitors.
Therefore my question: Can a violation of the power-down sequence damage the CPU, or is a correct sequencing only required for a correct reset?
The datasheet (IMX8MPIEC) only states the sequence, not the significance. The Evaluation board has no measures for this as far as I can see.
Solved! Go to Solution.
Strictly speaking, the worst scenario, when violating power supplies
requirements and restrictions is irreversible damage to the processor.
This looks as a very strict restriction for power down; really customers
can refer to NXP reference boards and use their schematic, even if some
sequence violations take place there. The reference designs were tested.
Thanks for the answer, this means I have to deal with this problem on my board, since switching the supply will happen. This leads to another question:
I could use PMIC_ON_REQ to initiate a power down from a voltage monitor in the 24V supply, bevore the 5v regulator is switched off.The capacitors in the 24V supply may be big enough to keep the 5V alive for the power-down sequence.
But the datasheets are not very clear on whether this signal is an open-drain-output on the CPU-Side or level/edge sensitive.
Is it possible to use PMIC_ON_REQ as "Enable" for the PMIC?