eTSEC IEEE 1588 Layer 2 support

[smazzux]

Dear Freescale community,

I am switching to Freescale after having used other processors for quite a long time (Zilog, Xilinx, ...), so please excuse if my understanding of the subject is still vague.

I am asking here since I was not able to find any answer by googling, by searching in this very forum nor by looking at the Processor Reference Manual (that I am still finding a bit difficult to read, to be honest)

I would like to know if the eTSEC in the P1025 (and probably other families, too) can do hardware timestamping of PTP over Ethernet (layer 2) frames (and not just over IP/UDP frames).

From this code it seems the case, but I would really like a confirmation

gianfar_1588.c - ptpv2d - IEEE 802.1AS / IEEE 1588 version 2 Precision Timing Protocol supporting so...

I still need to understand how to configure the eTSEC to recognize a particular type of message (if possible - it may also be the case it is timestamping a predefined set of messages both ingoing and outgoing)

Many thanks for any help you could provide, and best regards.

Giulio Mazzoleni

[lunminliang · Accepted solution]

Yes, eTSEC can do the hardware timestamping, it's performed on ethernet level, at the moment where frame was transmitted or received. The device does not generate ptp packets in hardware, this is responsibility of software, so from the hardware point view, there is no difference ptp over ethernet or ptp over UDP.

Outgoing timestamping is performaned when instructed in TxFCB. Here is link to P1025 documentation on FSL website:P1025 Product Summary Page

[smazzux]

Thank you Lunmin. And can you also confirm that the hw timestamps every incoming message and is responsability for the kernel to keep or flush the timestamp associated to the various messages?

I have yet to start implementing the PTP stack on the QorIQ, but I see that Alan Bartky has already done a good job with its ptpv2d.

Best regards,

Giulio

[lunminliang]

Yes, hardware performs timestamping for all incoming packets, interrupt may be generated to core (kernel driver etc) on recognition of PTP packet by filter rule match.

[smazzux]

It is probably done by filling the Tx Frame Control Block description, as depicted on the P1025 QorIQ Integrated Processor Reference Manual at page 1201.

And the CPU probably timestamps *every* incoming message and the packet parsing is done in a second step by the kernel driver (I was previously using a device that was overwriting timestamps on the fly so it had to know which packet to parse - here the parsing is only done for outgoing packets).

I may not be correct on all the aspects since I am looking for documentation right know, so please excuse me.

Best regards,

Giulio