“Is it necessary that the nodes shown in "lspci" output, have to be defined in device tree ?

取消
显示结果 
显示  仅  | 搜索替代 
您的意思是: 

“Is it necessary that the nodes shown in "lspci" output, have to be defined in device tree ?

1,485 次查看
avinashh
Contributor III

Hi,

“Is it necessary that the nodes shown in "lspci" output, have to be defined in device tree ? I have device tree file for P2041RDB. In that only one node is created for pci i.e. bus 0. Now I have customized the reference board and connected one pcie-pci bridge to bus 0 and four pci devices are connected to that bridge. So in my lspci output, six node is showing. So is it necessary that I have to declare it all in device tree.”

regards,

Avinash

标签 (1)
3 回复数

1,252 次查看
yipingwang
NXP TechSupport
NXP TechSupport

Hello Avinash,

No need to define PCIe devices in the device tree. In fact, only PCIe controllers are defined in the dts file.


Have a great day,
TIC

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

1,253 次查看
avinashh
Contributor III

Thanks for your response Yiping.

One thing I also want to clear is that if it is necessary to declare the pcie/pci devices, if so, how is the interrupt number assigned to them. I have a dts for pci controllrer bellow,

pci1: pcie@ffe201000 {
reg = <0xf 0xfe201000 0 0x1000>;
ranges = <0x2000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
0x1000000 0x0 0x0 0xf 0xf8010000 0x0 0x10000>;
compatible = "fsl,p2041-pcie", "fsl,qoriq-pcie-v2.2", "fsl,qoriq-pcie";
device_type = "pci";
#size-cells = <2>;
#address-cells = <3>;
bus-range = <0 0xff>;
clock-frequency = <33333333>;
interrupts = <16 2 1 14>;
fsl,iommu-parent = <&pamu0>;
fsl,liodn-reg = <&guts 0x504>;

pcie@0{
ranges = <0x2000000 0 0xe0000000 0x2000000
0 0xe0000000 0 0x20000000
0x1000000 0 0x0 0x1000000
0 0x0 0 0x10000>;
reg = <0 0 0 0 0>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
interrupts = <16 2 1 14>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = <

0 0 0 1 &mpic 41 1 0 0

0 0 0 2 &mpic 5 1 0 0

0 0 0 3 &mpic 6 1 0 0

0 0 0 4 &mpic 7 1 0 0 >;

};
};

The output of lspci -t is

-[0000:00]---00.0-[01-07]----00.0-[02-07]--+-01.0-[03]----00.0
                                                                  +-02.0-[04-05]----00.0-[05]--+-00.0
                                                                  |                                            +-01.0
                                                                  |                                            +-02.0
                                                                  |                                             \-03.0
                                                                  +-03.0-[06]----00.0
                                                                  \-04.0-[07]----00.0

When I execute the "lspci -vvv" command all my device are assigned with an interrupt number, how is this interrupt number assigned, how should I modify the interrupt number, cause i'm experiencing an interrupt failure when I run the device tester program. How should I do the interrupt mapping for this assembly?

0 项奖励
回复

1,253 次查看
yipingwang
NXP TechSupport
NXP TechSupport

Interrupt specifiers consists of 4 cells encoded as follows:

   <1st-cell>   interrupt-number
                Identifies the interrupt source.  The meaning
                depends on the type of interrupt.

                Note: If the interrupt-type cell is undefined
                (i.e. #interrupt-cells = 2), this cell
                should be interpreted the same as for
                interrupt-type 0-- i.e. an external or
                normal SoC device interrupt.

   <2nd-cell>   level-sense information, encoded as follows:
                    0 = low-to-high edge triggered
                    1 = active low level-sensitive
                    2 = active high level-sensitive
                    3 = high-to-low edge triggered

   <3rd-cell>   interrupt-type

                The following types are supported:

                  0 = external or normal SoC device interrupt
                      The interrupt-number cell contains
                      the SoC device interrupt number.  The
                      type-specific cell is undefined.  The
                      interrupt-number is derived from the
                      MPIC a block of registers referred to as
                      the "Interrupt Source Configuration Registers".
                      Each source has 32-bytes of registers
                      (vector/priority and destination) in this
                      region.   So interrupt 0 is at offset 0x0,
                      interrupt 1 is at offset 0x20, and so on.

                  1 = error interrupt
                      The interrupt-number cell contains
                      the SoC device interrupt number for
                      the error interrupt.  The type-specific
                      cell identifies the specific error
                      interrupt number.

                  2 = MPIC inter-processor interrupt (IPI)

                      The interrupt-number cell identifies
                      the MPIC IPI number.  The type-specific
                      cell is undefined.

                  3 = MPIC timer interrupt
                      The interrupt-number cell identifies
                      the MPIC timer number.  The type-specific
                      cell is undefined.

   <4th-cell>   type-specific information

                The type-specific cell is encoded as follows:

                 - For interrupt-type 1 (error interrupt),
                   the type-specific cell contains the
                   bit number of the error interrupt in the

                   Error Interrupt Summary Register.

Please also refer to "Advanced Interrupt Mapping" in  Device Tree Usage - eLinux.org .


Have a great day,
TIC

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

0 项奖励
回复