We have adjusted the BWC (Bandwidth/pause control bits of DMA mode register), but haven't seen any change. We always get one data byte. Thank you.
Todd
解決済! 解決策の投稿を見る。
Please check the value of DMAx_MRn[DAHE,SAHE] (RM Section 13.3.1).
Probably, you are trying to DMA data to FPGA register on the PCIe side of DMA. DMA doesn't burst if DAHE,SAHE != 0.
The source/destination transaction size calculations provided in RM Section 13.4.1.1 is only applicable to the case of DAHE,SAHE = 0.
Have a great day,
Pavel
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------
Please check the value of DMAx_MRn[DAHE,SAHE] (RM Section 13.3.1).
Probably, you are trying to DMA data to FPGA register on the PCIe side of DMA. DMA doesn't burst if DAHE,SAHE != 0.
The source/destination transaction size calculations provided in RM Section 13.4.1.1 is only applicable to the case of DAHE,SAHE = 0.
Have a great day,
Pavel
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------