How to configure QE port B pins as gpios in p1021

[amanagantivinod]

Hi All,

I am working on p1021rdb. I need to configure PB10 as gpio pin, I wrote gpios property as

gpios = <&qe_pio_b 42 0>; inside a device node.

then used following functions

of_gpio_count(),

of_get_gpio_flags(),

gpio_request(),

Here I am getting error in the of_get_gpio_flags() function call..

When I started debugging the this I came to know that QE gpio controller chip is added to the list of gpio chip controllers with only 32 gpios .

Ddue to this of_gpio_simple_xlate() is throwing error while comparing the below condition

if(gpiospec->args[0] >= gc->ngpio)

return -EINVAL;

what is the number that should be passed in the device tree to configure PB10 as gpio, is there any document that explains pin numbers and their corresponding gpio numbers in the QE gpio chip controller?

As the driver code supports only 32 gpios at max, how to port map pins? it is not like PA0 pin maps to 0, PB0 maps to 32 ??

Your help is appreciated.

[amanagantivinod]

Hi Podiatchev,

Thanks for your reply.

I understand that we need to create a node for each parallel I/O ports, and gpios property should use the proper proper port node's phandle, pin number as below..

gpios=<&qe_pio_X, pin_num, 0>

in my device tree there was only port-B node, I added  port-A and tried its pins as gpios its working... :smileygrin:

Thanks once again!!

[r8070z · Accepted solution]

Have a great day,

binding/powerpc/fsl/cpm_qe/gpio.txt says

#gpio-cells : Should be two. The first cell is the pin number and the second cell is used to specify optional parameters (currently unused).

as example see

lxr.free-electrons.com/source/arch/powerpc/boot/dts/mpc8569mds.dts

or

lxr.free-electrons.com/source/arch/powerpc/boot/dts/mpc8360rdk.dts

i.e. for PB10 it should be <&qe_pio_b 10 0>

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