How does the L3 cache mapping to memory in P4080DS, how the address was translated?

[peterzheng]

Hi,

Currently I am trying to run a program on Core 0 of P4080ds. I would like to restrict the program to only use 1/8 of the L3 cache?

May I know how could I achieve this?

Regards,

Peter Zheng

[scottwood]

The CPC can be partitioned by way.  If you are using the Embedded Hypervisor (Topaz), as your other questions suggest you are, this can be configured using the allocate-cpc-ways property in the hv config tree on the PMA node.

[peterzheng]

Thanks Scott. After partitioning the CPC, if I would like to do some testing, I am thinking about the following method, is this the right way?

(1) boot up the P4080DS into hypervisor, which has partitioned the CPC

(2) Start a bareboard project on CodeWarrior, for each core of P4080DS, one project was created

(3) Run the bareboard project on P4080DS

Will the test program follow the partition I created?

If not, how would you suggest to test the partition?

Regards,

Peter

[scottwood · Accepted solution]

I don't know if CodeWarrior can create standalone applications that run under the hypervisor -- I suggest starting a new thread with that in the subject to get the attention of someone who might know.  Certainly, you wouldn't be using CodeWarrior to actually run the project.  The hypervisor has to do that.

[peterzheng]

Thanks Scott.

I will try to start a new thread on this.

[lunminliang]

Hi,

The allocation or mapping is based on the physical address, and sets-ways-lines, the P4080RM.pdf does not detail information for this part. The basic idea is mapping through physical address to sets-ways-lines. As it's not one to one mapping, the replacement algorithm is used:

Configurable pseudo-least recently used (PLRU), streaming PLRU with aging,streaming PLRU without aging, and first-in/first-out (FIFO) replacement policies with programmable allocation policy and update options.

Have a great day,
Lunmin

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