Connecting P2020 to P2020 over eTSEC

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Connecting P2020 to P2020 over eTSEC

910 次查看
toddreed
Contributor I

I am looking to connect two P2020 processors together over their eTSEC connections.  My main limitation is that I need to keep all signals below 40Mhz.  As far as I can tell, my best bet is to use the MII interface at 2.5 or 25 MHz.  Can I just hook it up like this:

pastedImage_1.png

I would then tie the collision, carrier_sense, and rcv_error signals in the proper state to allow communication.

Is there anything wrong with this plan?

Thanks,


Todd

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720 次查看
r8070z
NXP Employee
NXP Employee


Have a great day,

Yes you can connect the P2020 in this way. Care must be taking in the setup and hold timings on the two MAC devices. See as example timing analysis in ZARLINK app note “Ethernet Switch MAC-to-MAC Connections”.

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720 次查看
toddreed
Contributor I

Hi Serguei,


Thank you for the confirmation and the timing warning.  I have been looking at the output delay, setup, and hold times, and the timing seems tricky for 100mbps operation.  For a 25Mhz clock, the period would be 40ns, the TX_CLK to data delay is 1-15ns, and setup and hold times are 10 ns.  If one TX_CLK to data delay is 15ns and then the following one is 1ns, there is only 26ns of valid data there.  To allow for 10ns setup and hold times, the RX_CLK edge would seem to have to be pretty precise!  Am I looking at something incorrectly, or is there any more accurate timing on the TX_CLK delay that could help?

Thanks,

Todd

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