I want to flush the L1 cache on my P2020 processor with the assembly instruction dcbf. In order to do that, I need to know where the cache L1 is (if I am not mistaken ?). But I don't find any L1 cache definition in my project and I was wondering if this is why I don't know the address or if this is kind of an automatic process made by the processor ?
Anyway, how can I retrieve the address of the L1 cache ?
Once retrieved, in order to flush it, I will do something like that:
# r1 = start of shared region
dcbf 0,r1 # flush line at address r1
Is it the rigth manner to proceed ?
Thank you a lot for your answers,
Ok, so after some verification with my probe, the routine does not work, I don't see my D-cache as totally flushed and invalidated.
I think I made a mistake while giving the argument to the dcbf instruction.
In C, I created a variable:
int i = 0;
// then I call the next routine (which is exactly the routine from my first message (with isync and msync at the end))
FlushDataCache((int)&i, (int)(&i + DATA_CACHE_FLUSH_48K/4));
I thought the dcbf instruction will find the D-cache according to i variable, and flush the line. I don't know what's wrong ?
Sorry to bother, thank you for your anwsers,
The cache addresses are setup by U-Boot and L1 is used to execute first stage boot loader. Anyway, if I may ask why do you want to flush L1 with your code? OS should take care it.