Hello Hymalai,
This register is used in the case of PAMU is enabled, users could program CPC registers CPCPIRn, CPCPARn and CPCPWRn to restrict allocation for several partitions when PAMU enabled, and this level of configuration is performed by hypervisor.
In the Soc each core has its own TLB, I think you could configure TLB entries to implement your purpose to allocate a specific partition of CPC as SRAM for each core.
Have a great day,
Yiping
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Do you plan to use part of the CPC as SRAM and the rest as L3 cache? I am afraid it's shared among cores.
Hi Lunmin,
I also have similar question? If I want to divide the CPC into 8 equal parts, and let each core use 1 part of CPC, how to achieve that? Is it through setting the register?
Regards,
Peter Zheng