Why the address of MIDRn in dts for s32r45 no offset

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Why the address of MIDRn in dts for s32r45 no offset

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aiweixin
Contributor IV

Hi,

    I find the address of SIUL2_0 MIDR1 in S32R45 rm file have 4bytes offerset.

aiweixin_2-1677564908060.png

    But, in arch/arm64/boot/dts/freescale/s32r45.dtsi, the address of SIUL2_0 MIDR1 no offset.

aiweixin_3-1677565033239.png

    In my opinion, why not as follow?

<MIDR_SIUL2_0 0 0x0 0x4009c004 0x0 0x08>

    Is it related to address alignment? I'm not sure.

    

 

 

 

 

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292 次查看
petervlna
NXP TechSupport
NXP TechSupport

Hello,

Since there are 2 MIDR registers, there must be an offset.

I do not know about the s32r45.dtsi but physically there is offset.

Simply check MIDR registers in debugger.

Best regards,

Peter

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