Hi.
I use TJA1128EVB to design LIN slave unit with S32K146EVB. I have some problems configurating the TJA1128G chip on this evalkit. I use tja1128 datasheet and aplication note and tja1128 NXP_example project but i am not able to configurate the tja1128. I would like to ask you kindly for checking of my approach. Seems i am missing something, not able to figure out what. Thanx a lot. Jan
0) TJA1128EVB supplied by 12V, S32K1146 supplied by usb, programmed by jtag
1) I consider the TJA1128 unconfigured in case that EN=1, STNB=1, RSTN=1 and RX=0
2) I switch off uart pins, switch on the LPSPI1 pins. SPI1 pins are wired to TJA1128
3) I am trying to write a configuration when MTPNV_STATUS_CONFIG_NVMPS_WRITE_EN and MTPNV_STATUS_CONFIG_NVERR_NOERROR are in True
I can read value 199, which is True for both status bits and 49 for configuration counter.
I supose SPI comm is ok. Anyway my SPI configuration:
SPI setting:
/* Initialize LPSPI 1 as master */
/*!
* LPSPI1 Clocking:
* ===================================================
*/
PCC->PCCn[PCC_LPSPI1_INDEX] = 0; /* Disable clocks to modify PCS ( default) */
PCC->PCCn[PCC_LPSPI1_INDEX] = PCC_PCCn_PR_MASK /* (default) Peripheral is present. */
|PCC_PCCn_CGC_MASK /* Enable PCS=SPLL_DIV2 (40 MHz func'l clock) */
|PCC_PCCn_PCS(6);
/*!
* LPSPI1 Initialization:
* ===================================================
*/
LPSPI1->CR = 0x00000000;
/* Disable module for configuration */
LPSPI1->IER = 0x00000000;
/* Interrupts not used */
LPSPI1->DER = 0x00000000;
/* DMA not used */
LPSPI1->CFGR0 = 0x00000000;
/* Defaults: */
/* RDM0=0: rec'd data to FIFO as normal */
/* CIRFIFO=0; Circular FIFO is disabled */
/* HRSEL, HRPOL, HREN=0: Host request disabled */
LPSPI1->CFGR1 = LPSPI_CFGR1_MASTER_MASK;
/* Configurations: master mode */
/* PCSCFG=0: PCS[3:2] are enabled */
/* OUTCFG=0: Output data retains last value when CS negated */ /* PINCFG=0: SIN is input, SOUT is output */ /* MATCFG=0: Match disabled */
/* PCSPOL=0: PCS is active low */
/* NOSTALL=0: Stall if Tx FIFO empty or Rx FIFO full */
/* AUTOPCS=0: does not apply for master mode */
/* SAMPLE=0: input data sampled on SCK edge */
/* MASTER=1: Master mode */
// frecuency(SCK) = (40Mhz/(2*LPSPI_TCR_PRESCALE) / (CCR_SCKDIV+2)
// frecuency(SCK) = (40M/2*32)/(8+2) = 62.5kHz
LPSPI1->TCR = LPSPI_TCR_PRESCALE(6)
|LPSPI_TCR_PCS(0)
|LPSPI_TCR_FRAMESZ(15)
|LPSPI_TCR_CPOL_MASK;
/* Transmit cmd: PCS3, 16 bits, prescale func'l clk by 4, etc */
/* CPOL=1: SCK inactive state is high */
/* !(CPHA=1: Change data on SCK lead'g, capture on trail'g edge) */ /* PRESCALE=6: Functional clock divided by 64*2=128 */
/* PCS=0: Transfer using PCS0 */ /* LSBF=0: Data is transfered MSB first */
/* BYSW=0: Byte swap disabled */
/* CONT, CONTC=0: Continuous transfer disabled */
/* RXMSK=0: Normal transfer: rx data stored in rx FIFO */
/* TXMSK=0: Normal transfer: data loaded from tx FIFO */
/* WIDTH=0: Single bit transfer */
/* FRAMESZ=15: # bits in frame = 15+1=16 */
LPSPI1->CCR = LPSPI_CCR_SCKPCS(4)
|LPSPI_CCR_PCSSCK(4)
|LPSPI_CCR_DBT(8)
|LPSPI_CCR_SCKDIV(8);
/* Clock dividers based on prescaled func'l clk of 100 nsec */
/* SCKPCS=4: SCK to PCS delay = 4+1 = 5 (500 nsec) */
/* PCSSCK=4: PCS to SCK delay = 9+1 = 10 (1 usec) */
/* DBT=8: Delay between Transfers = 8+2 = 10 (1 usec) */
/* SCKDIV=8: SCK divider =8+2 = 10 (1 usec: 1 MHz baud rate) */
/* recalculation with prescale 7 (64) => 31.25kHz */
LPSPI1->FCR = LPSPI_FCR_TXWATER(3);
/* RXWATER=0: Rx flags set when Rx FIFO >0 */
/* TXWATER=3: Tx flags set when Tx FIFO <= 3 */
LPSPI1->CR = LPSPI_CR_MEN_MASK
|LPSPI_CR_DBGEN_MASK;
/* Enable module for operation */
/* DBGEN=1: module enabled in debug mode */
/* DOZEN=0: module enabled in Doze mode */
/* RST=0: Master logic not reset */
/* MEN=1: Module is enabled */
4) write registers 0x10-0x15.
5) calculate crc considering init value 0x2c (evb has tja1128 mode G on it) and registers 0x10-0x15 and bytes 0x00 and 0x01. I calculate the crc following tja1128 datasheet and checking it with NXP_tja1128 example. I am convinced this part is ok.
uint8 crc = (uint8)DEF_CRC_TJA1128G; // depends on TJA1128 variant
uint8 sbc_register[8];
sbc_register[0] = (uint8)config_reg.system_reg.all; // system_register_content
sbc_register[1] = (uint8)config_reg.wake_reg.all; //wake_register_content
sbc_register[2] = (uint8)config_reg.ldo_reg.all; //ldo_register_content
sbc_register[3] = (uint8)config_reg.lin_reg.all; //lin_register_content
sbc_register[4] = (uint8)config_reg.watchdog_reg.all; //watchdog_register_content
sbc_register[5] = (uint8)config_reg.hvpmo_reg.all; //hvmpo_register_content
sbc_register[6] = (uint8)0; // additional fixed value to be used for calculation
sbc_register[7] = (uint8)1; // additional fixed value to be used for calculation
for (i=0; i<(uint8)8; i++){
data = sbc_register[i] ^ crc;
for (j=0; j<(uint8)8; j++){
if ((data & 0xFFu) >= (uint8)128){
data = (uint8)(data << (uint8)1); // shift left by 1
data = data ^ (uint8)0x2F;
}
else {
data = (uint8)(data << (uint8)1); // shift left by 1
}
}
crc = data;
}
crc = (uint8)(crc ^ (uint8)0xFF);
6) write crc to 0x30 TJA1128 register, turn off SPI, turn on UART
7) no reset was generated by TJA1128 to prove that configuration was successful. RX is stil in 0. Configuration counter is still 49. The TJA1128 configuration was not succesful.
despair and damnation
