PCF2131 reflow with battery

eric6 · ‎05-18-2023

Section 8 of the PCF2131 datasheet recommends not reflowing the part while biased with a battery. It also provides a way to use this assembly method by "a full \Q0 V' level Power supply \Qreset". From the datasheet it's unclear what this refers to. Is this a full power down (ie removal of battery) of the device? Is a reset through the I2C interface acceptable?

TomasVaverka · ‎05-26-2023

Hello Jacob,

The description in section 7.7.1 w.r.t. Fig 9 is only applicable to the very first startup/power-up of the part.

Assuming VBAT is present, subsequent power-down and power-up events on VDD will not cause oscillator to stop. The part will continue to function normally.

Note that the PCF2131 can only be powered-up via VDD. It will not power-up if only VBAT is present.

About the warning not to bias the part with a coin cell during reflow:

During assembly/reflow, even though VBAT pin is not “active”, there will still be a 3V connection to some circuitry inside and a leakage current path. Since the temperatures go up to +260C (much higher than operating temp of +85C), it may cause some internal circuit to be in an indeterminate state.

To get the chip back to a known state, a power-up ramp on VDD should be applied, which will trigger the POR circuit, which is in turn responsible for initializing all the registers and logic blocks to default values.

From here, the chip can be configured with the correct date/time and enabling battery-switchover function.

Best regards,

Tomas

View solution in original post

TomasVaverka · ‎05-21-2023

Hello Eric,

I am checking with the designer to clarify what this means. I will get back to you and update this thread early next week.

Best regards,

Tomas

TomasVaverka · ‎05-24-2023

Hello Eric,

The POR circuit is attached to VDD and the device has to be started with VDD present. So it should be VDD power up from 0 to 3.3V, regardless of VBAT voltage.

Best regards,

Tomas

JacobH · ‎05-24-2023

Hi Tomas,

I am working with Eric on this same issue,
we were concerned about the following datasheet section:

we are somewhat confused by the response that POR does not depend on VBAT because of section 7.7.1 (below) of the datasheet (why would the oscillator stop if VBAT were still high)

is it possible for us to communicate directly with the designer on this issue?

is this just resolved by power cycling VDD and manually toggling the OTP refresh bit?

TomasVaverka · ‎05-26-2023

Hello Jacob,

The description in section 7.7.1 w.r.t. Fig 9 is only applicable to the very first startup/power-up of the part.

Assuming VBAT is present, subsequent power-down and power-up events on VDD will not cause oscillator to stop. The part will continue to function normally.

Note that the PCF2131 can only be powered-up via VDD. It will not power-up if only VBAT is present.

About the warning not to bias the part with a coin cell during reflow:

During assembly/reflow, even though VBAT pin is not “active”, there will still be a 3V connection to some circuitry inside and a leakage current path. Since the temperatures go up to +260C (much higher than operating temp of +85C), it may cause some internal circuit to be in an indeterminate state.

To get the chip back to a known state, a power-up ramp on VDD should be applied, which will trigger the POR circuit, which is in turn responsible for initializing all the registers and logic blocks to default values.

From here, the chip can be configured with the correct date/time and enabling battery-switchover function.

Best regards,

Tomas

JacobH · ‎05-26-2023

Thank you Tomas, this clarifies things substantially