I2C bus specification (minimum rise/fall time) for PCA9544A

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I2C bus specification (minimum rise/fall time) for PCA9544A

749 Views
Danz1
Contributor III

Hi,

 

I would like to know if the I2C bus minimum rise/fall time of (20 + 0.1Cb)ns is a input or output signal requirement? 

If it is an input requirement, how does the bus capacitance affect the input circuitry? My understanding is that if the rise/fall time is too fast, it may trigger the spike suppressor in Fast mode. If that is the case, why not specify the minimum rise/fall time as 20ns instead?  

 In I2C Bus specification Revision 7.0, the minimum rise/fall time is no longer dependent on the bus capacitance. What is the reason?

Thank you.     

 

 

Danz1_0-1694504029953.png

Rgds

Danz

 

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5 Replies

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JozefKozon
NXP TechSupport
NXP TechSupport

Hi Dan,

the minimum rise/fall times are required to reduce electromagnetic interference due the fast rise/fall times.
UM10204 just follows the I2C spec. The bus capacitance may influence the EMI results. Longer cables usually have higher capacitance, and longer cables are more prone to induce voltage spikes.

JozefKozon_0-1694517520716.png

Please follow the requirements in the datasheet and other documents.

With Best Regards,

Jozef

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661 Views
Danz1
Contributor III

Hi Jozef,

Thanks for your reply.

Based on your info, am I right to say the minimum rise/fall time of (20 + 0.1Cb) ns in the PCA9544A is a output signal requirement? 

Thanks.

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653 Views
JozefKozon
NXP TechSupport
NXP TechSupport

Hi Dan,

the datasheet is meant for the PCA9544A. So the requirements are for input signal on the SDA and SCL pins. Other components connected to the I2C interface might have different requirements. Please check the datasheet of the other components for the signal requirements. 

With Best Regards,

Jozef 

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623 Views
Danz1
Contributor III

Hi Jozel,

I do not understand why PCA9544A, as a slave device, require the minimum rise/fall time to be (20 + 0.1Cb) ns? Why is the input trace capacitance has an effect on the minimum rise/fall time specification?

Thanks.

Rgds

Danz

 

 

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612 Views
JozefKozon
NXP TechSupport
NXP TechSupport

Hi Dan,

the waveforms on the SCL and SDA lines might be distorted, due to EMI built in the cables or PCB traces,  to the point that the PCA9544A doesn't recognize part of the signal or whole signal. Longer cables or PCB traces have usually higher capacitance. Larger bus capacitance is prone to be more vulnerable to EMI. The communication is then not possible.

With Best Regards,

Jozef 

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