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NXP Tech Blog

addiyi
NXP Employee
NXP Employee

Introducing SerDes tool for i.MX95 family. SerDes tool is part of Config tools for i.MX offering configuration and validation functionalities. It can be downloaded from Config Tools for i.MX Applications Processors

SerDes tool User Guide is part of  User Guide for Config tools for i.MX

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addiyi
NXP Employee
NXP Employee

DDR tool supports i.MX8M family, i.MX93 family, i.MX95 family and LX2160A\LX2162A. DDR tool is part of Config tools for i.MX offering configuration, inspection, optimization, vTSA, stressing and code generation. It can be downloaded from Config Tools for i.MX Applications Processors

DDR tool User Guide is part of  User Guide for Config tools for i.MX

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SimonZossak
NXP Employee
NXP Employee

The Enhanced Time Processing Unit (eTPU) is a programmable I/O controller with its own core and memory system running independently of the CPU. The eTPU Software Plugins are safety qualified, production-ready software drivers that deliver motor control functionality on the eTPU.

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bradloane
NXP Employee
NXP Employee

NXP’s S32N55 device is the first in NXP’s new 5nm S32N family of vehicle super-integration processors for central compute applications. We will walk through the main modules and features shown in the S32N55 block diagram to explain them in more detail.

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briancarlson
NXP Employee
NXP Employee

The S32N55 virtual prototype from Synopsys provides a comprehensive development platform for the S32N55 enabling software developers to debug and analyze their software efficiently, leading to faster turnaround and higher software quality. It includes the processing subsystem, the security subsystem, functional safety models, PCI Express communication interface, multi-port TSN Ethernet switch and CAN hub. 

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briancarlson
NXP Employee
NXP Employee

The S32N55 is the first member of the S32N family of vehicle super-integration processors.  It targets centralized, safe, real-time vehicle control in software-defined vehicles (SDVs).

 

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briancarlson
NXP Employee
NXP Employee

To support the transition to future vehicles where capabilities and features are defined with software code, rather than with hardware boxes, a new approach to design them is required. NXP's new S32N family targets the super-integration of vehicle functions for central compute applications in SDVs.

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addiyi
NXP Employee
NXP Employee

Memory validation supports i.MX RT devices and it is available on top of Peripherals tool for SEMC, FlexSPI and FCB components.

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joseOcampoHernandez
NXP Employee
NXP Employee

This article serves as an update to the MCU-Link Debug Probe Getting Started guide.

 

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Yongbing_Nan
NXP Employee
NXP Employee

Introduction

This is a brief introduction explaining the powertrain domain controller reference design integrated the BMS and VCU in one ECU based on S32K376 MCU. BMS system monitors battery voltage, temperature and fault status, among other parameters of the vehicle. VCU sample simulates pedal position, gear, sensors, among other functions of the vehicle. Software is developed based on Real-Time Drivers (RTD). The reference design is intended to provide a mechanism for easy customer evaluation of the Arm Cortex-M7@320MHz four cores MCU, and to facilitate BMS and VCU hardware and software development. OTA and bootloader function are also integrated into this reference design which make program upgrade feasible. Fig1 shows the s32k376 system block diagram.

Yongbing_Nan_0-1706686417238.png

Fig.1: S32K37x system block diagram

Solution overview

The Figure 2 shows the system block diagram. Analog front-end(AFE) MC33774 is used to monitor battery status. Gateway MC33665 is used to transfer SPI signal to transport protocol link(TPL3). SBC FS2633 supply power for S32K376 and external devices. High-side device(HSD), low-side device(LSD) and Multiple Switch Detection Interface(MSDI) are used for vehicle control unit(VCU) function. CAN, LIN, UART are used to communicate with other ECUs. Real-Time clock(RTC) is used to read real time for BMS state of charge(SoC) calculation.

Yongbing_Nan_0-1706783936004.png

Fig.2: system block diagram

The Figure 3 shows the whole hardware battery monitor unit(BMU) board and lists each type of device. The detailed connector interface can be found in the schematic.

Yongbing_Nan_0-1706689281233.png

Fig.3: hardware BMU board 

Hardware design

Please refer the doc AN747202-S32K39_37 MCUs Hardware Design Guidelines(0.2).pdf and S32K376 BMU and VCU Integration User Manual.pdf for the detailed hardware design.

MC33774: 18 Channel Li-Ion Battery Cell Controller IC ASIL D

MC33665: General Purpose BMS Communication TPL Transceiver and CAN FD Gateway

Software design

S32K376 BMS&VCU software is based on AUTOSAR drivers, including SW32K3 RTD, MC33774 BCC, MC33665 TPL PHY and SBC. It provides a series of AUTOSAR specific API to facilitate the BMS application designer to implemented the BMS application.

The Figure 4 shows the S32k376 BMS&VCU solution software block diagram. BMS function run on function core CM7_0, VCU function runs on lockstep core CM7_2, and monitor another two cores through IPCF. OTA and reserved OBC function run on the function core CM7_1. Bootloader and hardware OTA update application firmware. GUI display BMS and VCU information. All driver are based on AUTOSAR RTD.

Yongbing_Nan_0-1706767914149.png

Fig.4: BMS and VCU software block diagram

  • Startup process and project structure

BMS, VCU and OTA run on different cores. The core0 is startup core, it starts up first than core1 and core2. The core0 initial all of system and peripheral clock and setup GPIO status. Using the CM7-x-ENABLE field of IVT boot configuration word(BCW) to disable core1 and core2 for avoiding core1 and core2 to execute any uninitialized peripheral. The core1 and core2 start up after core0 writes the correct address to the MC_ME module and enables clock.

The three cores projects are completely independent. Each core has by itself a startup file, linker file and memory layout. After compiling, three core's elf file will be generated. One elf file with three cores project is feasible, but we don't implement it here.

  • Multi core communication

Inter-Platform Communication Framework (IPCF) is a subsystem which enables applications, running on multiple homogenous or heterogenous processing cores, located on the same chip or different chips, running on different operating systems (AUTOSAR, Linux, FreeRTOS, Zephyr, etc.), to communicate over various transport interfaces (Shared Memory etc.)

IPCF is designed for NXP embedded systems and features low-latency and tiny-footprint. It exposes a zero-copy API that can be directly used by customers for maximum performance, minimum overhead and low CPU load. The driver ensures freedom from interference between local and remote shared memory by executing all writing operations only in the local memory domain. CPU to CPU and directed interrupts are used to implement this function. BMS and VCU run in different cores, we use IPCF to send their framing data through CAN.

  • Basic workflow of project

Figure 5 shows the project program work flow and lists the schedule time of each task.

Yongbing_Nan_0-1706772758179.png

Fig.5 Project programming flow diagram

  • SAF function

The S32K396 Safety Software Framework (S32K396 SAF) is a software product which contains software components establishing the safety foundation for customer’s safety applications compliance with ISO 26262 functional safety. S32K396 SAF is a framework that implements the device safety concept system solution. Due to the SAF is not free for customer, for detailed information please refer S32K396_SAF_Safety_Manual.pdf and package S32K396_SAF_0.8.0. Figure 6 lists each component of SAF.

Yongbing_Nan_1-1706773286725.png

Fig.6 SAF component

  • BMS safety library function

This is the S32K3 BMS SL SDK DEMO AUTOSAR 4.4 Version 1.0.0 release for the S32K3 platform. The Bcc_775a_SL, Bcc_774a_SL, Bcc_772c_SL and Bms_TPL3_SL_E2E libraries included in this release have DEMO quality status in terms of testing and quality documentation. Demo libraries are not qualified and contain partial feature set. It is not intended to be used in production This Demo version of the Safety Library is delivered in binary format and it's intended for evaluation purposes only. Due to the BMS safety library(SL) is not free for customer, for detailed information please refer RTD_BCC_774A_SL_UM.pdf and package SW32K3_BMS_SL_SDK_4.4_1.0.0_DEMO.

S32k376 BMS&VCU solution enables external safety mechanisms1, 2 , 3, 5 to monitor battery status.  Customers cannot use it unless they purchase the BMS SL installation package. For detailed setup step, please refer to quick start guide document in NXP.com.

  • Project memory map

S32K376 has 6M flash space to store binary code that consist of three 2MB flash blocks. Bootloader is placed in the first flash block, and the three cores projects are divided into one flash block via link file and MPU. HSE is used for code switching in block 1 and block 2. A/B swap HSE firmware and secure boot assist flash(SBAF) is necessary to enable hardware OTA function.

Yongbing_Nan_0-1706773940160.png

Fig.7 s32k376 BMS and VCU project memory map

  • Hardware OTA

The project integrates OTA in Core1 and schedules it using FreeRTOS. The low level driver is based on Ethernet. For users of the S32K376 device with OTA enabled, the passive region can be read and written, and when an OTA update is performed, the new APP is always written to the passive region, but no program can execute in that region. The process of A/B swap is executed by hardware, no memory copy.

image.png

Fig.8: S32K376 hardware OTA update flow

  1. The OTA update agent-APP_V1 is first downloaded to the active block1(0x00600000) via the debugger and then starts running.
  2. When the OTA update is performed, the PC sends the new version of the OTA update agent-APP_V2, APP_V1 receives the binary file of APP_V2 and writes it to the block2(0x0800000) which is in passive.
  3. After partition swap and reset, the APP_V1 switchs to passive region, the new APP_V2 switchs to active region and runs.
  • Bootloader 

Bootloader is provided to update the application via CAN bus in case there are no tools to download the application directly. S32k396_Bootloader is a standalone project which will be flashed on the flash block0, shown in Figure 28. The IVT information appears on the low address, so the code always starts up from the block0. Application is downloaded on flash block1 by bootloader.

GUI

This GUI displays data transmitted from BMS and VCU system via CAN bus. Hands-on instructions are listed below. For a detailed introduction, please refer to S32K376 BMU and VCU Integration User Manual.pdf.

Yongbing_Nan_0-1706776849941.png

Fig.9: S32K376 BMS and VCU GUI

S32K376 BMS and VCU demo platform

The figure 10 shows the s32k376 BMS and VCU demo platform. To see the detailed set up guide, please refer S32K376 BMSVCU_QSG.pdf and Getting started page.

mmexport1687150733686-cut_allD_bms_only_modify.jpg

Fig.10: S32K376 BMS demo platform

More information can be found here:

S32K376 Battery Management System (BMS) and Vehicle Control Unit (VCU)

S32K39/37 Microcontrollers for Electrification Applications

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jana_t
NXP Employee
NXP Employee

  • MicroPython firmware upload via LinkServer
  • REPL communication though PuTTY
  • VS Code for MicroPython code
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addiyi
NXP Employee
NXP Employee

DDR tool supports i.MX8M family, i.MX93 family and LX2160A\LX2162A. DDR tool is part of Config tools for i.MX offering configuration, inspection, optimization, vTSA, stressing and code generation. It can be downloaded from Config Tools for i.MX Applications Processors

DDR tool User Guide is part of  User Guide for Config tools for i.MX

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APraveen
NXP Employee
NXP Employee

The demo showcases ultra low power usage on a Sensor Hub and runtime power usage for SoC using Evaluation Kit (EVK) power measurement capability on i.MX8ULP.

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addiyi
NXP Employee
NXP Employee

DDR tool supports i.MX8M family, i.MX93 family and LX2160A\LX2162A. DDR tool is part of Config tools for i.MX offering configuration, inspection, optimization, vTSA, stressing and code generation. It can be downloaded from 

https://www.nxp.com/design/designs/config-tools-for-i-mx-applications-processors:CONFIG-TOOLS-IMX

DDR tool User Guide is part of  User Guide for Config Tools for i.MX

 

 

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nxp-admin
NXP Employee
NXP Employee

Introduction:

Processing requirements for automotive ECUs has been on the rise. This has resulted in automotive microprocessors demanding more power while also going to smaller manufacturing nodes.

This trend presents a two-fold challenge for a power supply designer:

  • Deliver a high power
  • Deliver the higher power at a smaller allowed tolerance

Board space and budgets are constrained so the power supply designer needs to solve the above 2 challenges while staying below the space and cost budgets.

On top of this, there is a trend to meeting functional safety requirements for the system of which the power supply is a critical part of. This blog presents considerations a designer needs to take while designing such a power supply and how the PF53 core supply regulator from NXP Semiconductors offers a convenient solution.

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Andrei_Terechko
NXP Employee
NXP Employee

Daruma is a design pattern for multi-channel redundant automated driving systems. The video demonstration of the Daruma’s proof of concept shows improvements of automated vehicle’s safety and availability in the CARLA simulator.

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rares_butilca
NXP Employee
NXP Employee

Whether you are participating at the NXP Cup competition or simply passionate about self-driving cars, try using MBDT to program a microcontroller to drive your car on a track. In this article you will find a model you can use as a starting point for your application.

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shaojun_wang
NXP Employee
NXP Employee

This document shows how to debug i.MX8MP uboot with TRACE32 debugger.
For Linux debug, please check https://community.nxp.com/t5/Blogs/Debug-i-MX8MP-Linux-with-TRACE32/ba-p/1582382

  1. Build uboot
  2. Run uboot and get relocate offset
  3. TRACE32 script
    3.1 Data.LOAD.Elf
    3.2 relocate offset
  4. Attach i.MX8MP board to TRACE32 debugger

 

 

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nxp-admin
NXP Employee
NXP Employee

Providing a low-cost and single-wire scheme, it comes as no surprise that LIN bus systems are increasingly used in the body domain of vehicles. Typical LIN applications, such as seat control, lighting, and steering wheel, are generating more requests for smaller bill of material and lower costs on system level. NXP’s latest smart QUAD LIN transceiver SJA1124 provides an innovative way to connect LIN bus to MCU for the electronic control units (ECUs) in the car to meet the aforementioned needs.

The number of LIN channels per application is increasing as the use of the LIN bus becomes widespread. Unlike the increasing number of LIN nodes, the space and bill of material for these applications are often shrinking to save cost. NXP’s SJA1124 is a QUAD LIN transceiver with integrated commander terminations, LIN controllers, and an SPI-to-LIN bridge. These features bring scalability and flexibility to the application network and MCU option, providing you with varied benefits.

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addiyi
NXP Employee
NXP Employee

DDR tool supports i.MX8M family and LX2160A\LX2162A. DDR tool is part of Config tools for i.MX offering configuration, inspection, optimization, vTSA, stressing and code generation. It can be downloaded from 

https://www.nxp.com/design/designs/config-tools-for-i-mx-applications-processors:CONFIG-TOOLS-IMX

DDR tool User Guide is part of  User Guide for Config Tools for i.MX

 

 

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shaojun_wang
NXP Employee
NXP Employee

This article shows how to attach TRACE32 to i.MX8MP Linux and how to debug Linux with it.

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4 0 7,156
brendonslade
NXP TechSupport
NXP TechSupport

When running firmware v3.xxx onwards, MCU-Link uses WinUSB, so make sure your firmware matches a compatible MCUXpresso IDE version.

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2 0 4,135
tristan_mcdaniel
NXP TechSupport
NXP TechSupport

With the introduction of the new GreenBox 3 real-time development platform, NXP offers a game-changing platform that promotes ECU consolidation for enabling the future of automotive electrification. In this post, we will explore a consolidated ECU demo created around the GreenBox 3 and explain what advantages the GreenBox 3 offers for each of these use cases and why you may want to consider an ECU consolidated design.

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shaojun_wang
NXP Employee
NXP Employee

We already have application note AN13336 about running TFLM micro_speech example on Tensilica HiFi4 DSP on i.MX 8M Plus EVK.


In this document, TFLM micro_speech example will be upgraded to support i.MX DSP remote processors driver in newer Linux kernel, patch to support i.MX8QXP/i.MX8QM MEK will be provided, steps about how to download and install toolchain, how to build and run the example will be listed.

Hardware: i.MX8MP EVK, i.MX8QXP MEK, i.MX8QM MEK.
Software: Linux 5.15.52, TensorFlow Lite Micro

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kenli
NXP Employee
NXP Employee

Security is becoming more and more important in automotive products and related designs. The attachment shows how to perform simple verification of the secure boot process based on LSDK2108 and LX2160ARDB.

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xiaocong_fu
NXP Employee
NXP Employee

Step by step: load fusion fw to 8ulp flash


In this article, I'd like to share the steps to run fusion dsp fw in 8ulp, including all the issues I have encountered.

Pre-steps

To follow the steps, you will need:

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janna_garofolo
NXP Employee
NXP Employee

The race is on

The automotive industry is being revolutionized by innovations in efficient energy management, new vehicle architectures and software-defined vehicles (SDVs).  Automakers are racing to develop new solutions, taking advantage of these paradigm shifts in the market to establish themselves as innovators and to secure competitive positioning for their products.   

Market adoption of electrified vehicles is ramping quickly, propelled by government legislation for improved efficiency and reduced carbon emissions.  Vehicle networks have become increasingly complex, and manufacturers are recognizing significant opportunities to reduce cost, vehicle weight and development cycle times by moving to domain and zonal architectures that consolidate functions into fewer electronic control units with increased processing power.  Software-defined vehicles, which take full advantage of these new vehicle architectures, will provide life-long upgrade possibilities, resulting in vehicles that improve in performance over their lifetime and enable new revenue streams for vehicle manufacturers. 

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Eli_H
NXP Pro Support
NXP Pro Support

The RT685-AUD-EVK allowed me to validate my custom frontend circuitry and get started on other critical DSP software development.  I was able to connect the piezoelectric saddle pickups on my engineering guitar into the test bed via the custom daughtercard. From here I can focus on firmware in the MCU and DSP cores in the RT685. 

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kyledando
NXP Employee
NXP Employee

Please find document which is missing in the latest SDK bundle location for RT devices \docs\wireless\Release Notes.

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curt_hillier
NXP Employee
NXP Employee

The new S32Z and S32E automotive real-time processor families supercharge real-time vehicle compute and control applications. This article highlights how the complementary S32G vehicle network processor for service-oriented gateways, combined with the S32Z and S32E real-time processor can enable new automotive applications. Combining real-time compute with secure cloud connectivity supports advanced sensing, processing and control applications that can adapt with the life of your vehicle.

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