TDA8035 external clock synchronous mode.

[sylvainbouriot]

Hello,

am using TDA8035 chip as interface between smart card reader and micro controller. for synchronous and asynchronous card with a external clock generated by a micro-controller.

IN datasheet, we could read the follow sentence: "It is mandatory when an external clock is used, that the clock is applied on XTAL1 before CMDVCCN falling edge"

For asynchronous mode, it's not a problem.
But for synchronous mode, it's a problem, because, if  microcontroller send clock before CMDVCC falling edge, it will be not synchronized with card. (for example Microcontroller send 8 clocks, and card will receive 7 clocks (because card VCC is not yet active )

Have you any suggestion?

Sylvain

[jeff_ho]

Hello,

In the Fig.35 of AN10997, there is a capacitor, C10(56pF), between MCU and TDA8035/XTAL1. see below,

In the access process of the synchronized card, the MCU shall send the CLK signals. The level in each CLK signal is from low to high. So after the last CLK signal, the level of CLK is low. But since there is a pull-high circuit inside the TDA8035/XTAL1 and a C10 capacitor, the level of CLK signal will be pulled high after 56us.

This will cause the next card access process to lack a CLK signal because the level of the CLK signal is high at first.

Can I know what is the purpose of C10? Can I replace it with a resistor?

Thank you.

Best Regards,

Jeff

[Youssef_Houiti]

Recommendation for the clock C3 mangement:

- Clear CMD_VCC

- 50 cycles :

clear C3

wait 1µs

Set C3

wait 1µs

- Wait 3ms

- 12 cycles:

clear C3

wait 1µs

Set C3

wait 1µs

[Jonathan_Iglesias]

Dear Sylvain Bouriot,

the role and concept of the clock is quite different in the sync and async card case. For synchronous cards (s9, s10, i2c) clock is anyway coming from MCU so we have only external clock here because the MCU controls generates clock (assert and de-assert line).

Strictly speaking text "It is mandatory when an external clock is used, that the clock is applied on XTAL1 before CMDVCCN falling edge" is relevant for asynchronous card activation when external clock signal is used.

To activate a synchronous card the external clock doesn't need to be applied to the XTAL before CMDVCCN goes low,

but here we have something else...

the first 12 cycles will not be transferred (TDA needs to adjust internal state machine) so after this 12 cycles clock will pass TDA. this is something we have to take care with sync card activation.

BR

Jonathan