PN5180 DPC correlation test

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PN5180 DPC correlation test

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Pablo_192989
Contributor II

Hello
During the DPC calibration process I get an abnormal response, my current situation:
Customized board with an ESP32 and the PN5180 among other things, the components are inside the antenna (65x58mm) the reader is able to read the cards at about 5cm and the symmetrical tuning of the antenna is as follows according to the nanoVNA:

antenna tuning.png

The response to PICC and metal is shown below:

PICCmetal.png

I use my own library to control the PN5180, to perform the DPC correlation test I leave the DPC active and set the DPC_AGC_GEAR_LUT_SIZE to 1 so that it loads the value of the first position of the LUT (Note contained in AN11742 in point 1.2.1.1 Bit 0: Enable DPC). Up to this point everything works as expected, but when reading the AGC and current, instead of increasing the closer I get, the opposite happens, the current and AGC decrease. Any idea why this occurs?

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Kan_Li
NXP TechSupport
NXP TechSupport

Hi @Pablo_192989 ,

 

Thanks for the information! but I could not see the impedances under each condition, so I could not say if the tuning is good or not, but as you know, the impedance in case of the “symmetrical” tuning always decreases, so please check it from your side, and if the impedance would not decrease, you might have to redo the tuning according to AN11741.

 

Hope that makes sense,

 

Have a great day,
Kan


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Pablo_192989
Contributor II

 

Hello,
The graphs with the values corresponding to the original query are the following:

vacio.pngmetal.pngpicc.png

I managed to solve the original problem by detecting that the use of a 330nH coil did not comply with being greater than the size of the antenna:

antenna.png

With that change I managed to fix the problem with the correlation test but I would like to reduce the losses in some way, my current coil is the MCKK2012TR47M (0805in 470nH 3.1A 20% 32mohm).

new.png

I know it's not well tuned yet but, it's just to show the losses.

regards

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Kan_Li
NXP TechSupport
NXP TechSupport

Hi @Pablo_192989 ,

 

Is it possible to share the sch file regarding the antenna part? I have no idea about which part is replaced with the MCKK2012TR47M.

 

Thanks for your patience!

 

Have a great day,
Kan


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Pablo_192989
Contributor II

Hi @Kan_Li

The reference corresponds to coils L2 and L3.

Pablo_192989_1-1644433303807.png

The values of the capacitors are not adequate and I am in the process of adjusting them, but I am not able to reduce the losses.

To illustrate the problem a little more, I attach an image of my PCB layout and the many things inside the antenna (As I have verified, the influence of the coil chip antenna is very high)

Pablo_192989_2-1644433321044.png

Any guidance or comment is appreciated.

Greetings.

 

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Kan_Li
NXP TechSupport
NXP TechSupport

Hi @Pablo_192989 ,

 

Thanks for the clarification! For placing components inside the antenna, we recommend keeping distance between large piece of GND plane and the antenna as big as possible if you have to use it inside the loop, and also orthogonal crossing on another layer under the antenna is recommended if you have to do so.

 

Please kindly refer to https://www.nxp.com/video/nfc-antenna-design-6-emc-related-design:ANTENNA-EMC-DESIGN-VIDEO for more details.

 

Hope that helps,

 

Have a great day,
Kan


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Pablo_192989
Contributor II

I forgot
I would also like to know if the deformation of the loop could be corrected in some way, I suppose that the distortion is due to the components located inside the antenna.
Greetings.

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