Hardware reset for CLRC663

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Hardware reset for CLRC663

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Danz1
Contributor III

Hi,

May I know the maximum time interval that the IC will be ready after PDOWN transits from High to Low? 

Danz1_0-1678790254257.png

Thanks.

 

Rgds

Danz

 

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KellyLi
NXP TechSupport
NXP TechSupport

Hello @Danz1 

Thanks for contacting us and interested in the NXP products.
I also haven't been able to find any specific data for the time intervals, which would be hard to test out. But it shouldn't be very long, more than 10 microseconds should be fine.
Anyway, I'll consult with the R&D team for that. I'll keep update you if any news.


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