CLRC663 EMD suppression (ISO14443)

[tomh]

Hello,

while working with the CLRC663 chip I came across the RxCtrl register and saw the EMD_Sup bit.

I pretty much understand the EMD behaviour in general.

But what I don't understand is how the chip can be SURE that the error which appeared in the first 3 bytes is EMD related?

I know that there is a minimum time definition in which the PICC is not allowed to create any disturbance before sending the response. But the time before that (in which the PICC is allowed to disturb the field) can be so much longer (Frame Waiting Time).

Can anyone explain this to me?

Thanks in advance.

Best regards, Tom

[estephania_mart]

Hello,

Sorry for the inconvenience, but I'm not sure I fully understand what you need. Could you please help me with the source where you mention that the chip is sure? Could you please help me with more details so I can try to verify for further information about this?

Regards,

Estephania

[tomh]

Hello,

thanks for the reply. Basically I just want to understand this feature (EMD_Sup) of the RC663. What I actually need to know is if and how I can rely on that feature? Can there be a misinterpretation of the EMD? How can the chip be sure that the received data (which can be EMD) is not an actual answer from the chip?

BR, Tom

[estephania_mart]

Hello,

Sorry but the only information I was able to locate is that if an error occurs within the first three bytes or the frame is < 3 bytes, this frame is seen as EMD and ignored. If RxForceCRCWrite is set, the FIFO should not be read out before three bytes are written into. The FIFO is cleared automatically in case of an EMD error. A collision is treated as error.

Regards,
Estephania